verilog-codes-/randomization.sv at master · ayusdixit/verilog-codes- · GitHub

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 //randomization  in system verilog

class random ;
  rand bit [2:0] a,b ;
  task display();
  $display(" a =%d  , b =  %d  " , a , b);
  endtask
    endclass

program main ;
  random randd ;
  initial
    begin

      randd = new();
      repeat(10)
      begin
        randd.randomize();
        randd.display();


      end


    end

endprogram


//using randc

class random ;
  randc bit [2:0] a,b ;
  task display();
  $display(" a =%d  , b =  %d  " , a , b);
  endtask
    endclass

program main ;
  random randd ;
  initial
    begin

      randd = new();
      repeat(10)
      begin
        randd.randomize();
        randd.display();


      end


    end

endprogram