arch/mips/jz4780: Add HDMI EDID parsing and dynamic display modes

This commit introduces EDID reading and parsing to the JZ4780 display
driver, replacing hardcoded resolution limits with dynamic mode selection
based on the connected display's capabilities.

Specific changes include:
  - Implemented I2C DDC master communication for the HDMI controller to
    read EDID blocks from monitors.
  - Added dynamic mode selection to calculate bandwidth and pick the best
    supported resolution, prioritizing the EDID preferred mode.
  - Dynamically allocated framebuffer bounds (g_planeinfo and g_videoinfo)
    based on parsed EDID dimensions.
  - Configured GPIO pin multiplexing for HDMI power, DDC, and control pins
    (POWER_EN, CEC, SCL, SDA) to enable display power and communication
    on the CI20 board.

Signed-off-by: Lwazi Dube <lwazeh@gmail.com>

Author: ldube

Documentation/platforms/mips/jz4780/boards/mips-creator-ci20/index.rst

@@ -21,7 +21,7 @@ CPU1         No     1.2GHz MIPS32 processor
 RAM          Yes    256MiB
 ADC          No
 Audio        No
-Display      Yes    HDMI (EDID not yet supported)
+Display      Yes    HDMI
 DMA          No
 Ethernet     Yes    Fast Ethernet (DM9000)
 GPIO         Yes

arch/mips/include/jz4780/chip.h

@@ -89,6 +89,15 @@
 
 #define JZPMC_BASE          0xb0000000
 
+#define JZ_EXTCLK           48000000U
+
+#define PCR_PLLM(r)         ((r >> 19) & 0x1FFF)
+#define PCR_PLLN(r)         ((r >> 13) & 0x3F)
+#define PCR_PLLOD(r)        ((r >> 9) & 0xF)
+
+#define CPMPCR_REG          (JZPMC_BASE + 0x14)
+#define CPVPCR_REG          (JZPMC_BASE + 0x1c)
+
 #define CLKGR0_REG          (JZPMC_BASE + 0x20)
 #  define CLKGR0_OTG0       (1 << 2)
 #  define CLKGR0_UHC        (1 << 24)
@@ -111,11 +120,17 @@
 
 #define LP1CDR_REG          (JZPMC_BASE + 0x54)
 #  define LPCDR_VAL         0x15
-#  define LPCS_VPLL         0X80000000
+#  define LPCS_MPLL         0x40000000
+#  define LPCS_VPLL         0x80000000
 #  define CE_LCD            (1 << 28)
 #  define LCD_BUSY          (1 << 27)
 
 #define HDMICDR_REG         (JZPMC_BASE + 0x8c)
+#  define HPCS_SCLK_A       0x00000000
+#  define HPCS_MPLL         0x40000000
+#  define HPCS_VPLL         0x80000000
+#  define CE_HDMI           (1 << 29)
+#  define HDMI_BUSY         (1 << 28)
 
 #define SRBC_REG            (JZPMC_BASE + 0xc4)
 #  define SRBC_UHC_SR       (1 << 14)