boards/arm/stm32u3: Add NUCLEO-U3C5ZI-Q support

initial support for NUCLEO-U3C5ZI-Q

Assisted-by: OpenAI Codex:gpt-5
Signed-off-by: raiden00pl <raiden00@railab.me>

Author: raiden00pl

Documentation/platforms/arm/stm32u3/boards/nucleo-u3c5zi-q/index.rst

@@ -0,0 +1,30 @@
+======================
+ST NUCLEO-U3C5ZI-Q
+======================
+
+.. tags:: chip:stm32, chip:stm32u3, chip:stm32u3c5
+
+The `NUCLEO-U3C5ZI-Q <https://www.st.com/en/evaluation-tools/nucleo-u3c5zi-q.html>`_
+is an STM32 Nucleo-144 board featuring an STM32U3C5ZI microcontroller with
+2 MiB of Flash and 640 KiB of SRAM.  The board includes an ST-LINK debugger
+and programmer with a virtual COM port.
+
+Clocking
+========
+
+NuttX runs at 96 MHz from the internal MSIRC0 oscillator.  The initial port
+runs as a flat, nonsecure image with TrustZone disabled.
+
+Configurations
+==============
+
+nsh
+---
+
+Configures the NuttShell with USART1 as the serial console.
+
+jumbo
+-----
+
+Enables a broad set of NuttX features to provide additional build and runtime
+coverage.

arch/arm/src/stm32u3/stm32u3xx_rcc.c

@@ -26,6 +26,8 @@
 
 #include <nuttx/config.h>
 
+#include <assert.h>
+
 #include <arch/board/board.h>
 
 #include "arm_internal.h"
@@ -34,6 +36,25 @@
 #include "hardware/stm32_flash.h"
 #include "hardware/stm32u3xx_pwr.h"
 
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
+
+static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
+              "Configure BOARD_LOOPSPERMSEC to a non-default value");
+
+/* Allow up to 100 milliseconds for each clock or regulator transition. */
+
+#define CLOCK_READY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
+
+#ifndef STM32_BOARD_USEMSIS
+#  error stm32_stdclockconfig() requires MSIS board configuration
+#endif
+
+#endif
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -42,68 +63,127 @@
  * Name: stm32_stdclockconfig
  *
  * Description:
- *   Configure the STM32U3 system clock from MSIRC0 at 96 MHz.
+ *   Configure the STM32U3 system clock from the settings in board.h.
  *
  ****************************************************************************/
 
+#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
 void stm32_stdclockconfig(void)
 {
   uint32_t regval;
+  volatile int32_t timeout;
 
   /* The EPOD booster and voltage scaling control require the PWR clock. */
 
   modifyreg32(STM32_RCC_AHB1ENR2, 0, RCC_AHB1ENR2_PWREN);
 
-  /* Supply the EPOD booster from undivided MSIS. */
+  /* Select the board regulator and wait until the transition completes. */
+
+  modifyreg32(STM32_PWR_CR3, PWR_CR3_REGSEL, STM32_PWR_CR3_REGSEL);
+  for (timeout = CLOCK_READY_TIMEOUT; timeout > 0; timeout--)
+    {
+      if ((getreg32(STM32_PWR_SVMSR) & PWR_SVMSR_REGS) ==
+          STM32_PWR_CR3_REGSEL)
+        {
+          break;
+        }
+    }
+
+  if (timeout == 0)
+    {
+      return;
+    }
+
+  /* Configure and enable the EPOD booster. */
 
   regval  = getreg32(STM32_RCC_CFGR4);
   regval &= ~(RCC_CFGR4_BOOSTSEL_MASK | RCC_CFGR4_BOOSTDIV_MASK);
-  regval |= RCC_CFGR4_BOOSTSEL_MSIS;
+  regval |= STM32_RCC_CFGR4_BOOSTSEL | STM32_RCC_CFGR4_BOOSTDIV;
   putreg32(regval, STM32_RCC_CFGR4);
 
-  modifyreg32(STM32_PWR_VOSR, 0, PWR_VOSR_BOOSTEN);
-  while ((getreg32(STM32_PWR_VOSR) & PWR_VOSR_BOOSTRDY) == 0)
+  modifyreg32(STM32_PWR_VOSR, 0, STM32_PWR_VOSR_BOOST);
+  for (timeout = CLOCK_READY_TIMEOUT; timeout > 0; timeout--)
+    {
+      if ((getreg32(STM32_PWR_VOSR) & PWR_VOSR_BOOSTRDY) != 0)
+        {
+          break;
+        }
+    }
+
+  if (timeout == 0)
     {
+      return;
     }
 
-  /* Select voltage scale 1 and wait until it is active. */
+  /* Select the board voltage scale and wait until it is active. */
+
+  modifyreg32(STM32_PWR_VOSR, PWR_VOSR_R1EN | PWR_VOSR_R2EN,
+              STM32_PWR_VOSR_RANGE);
+  for (timeout = CLOCK_READY_TIMEOUT; timeout > 0; timeout--)
+    {
+      if ((getreg32(STM32_PWR_VOSR) &
+           (PWR_VOSR_R1RDY | PWR_VOSR_R2RDY)) ==
+          STM32_PWR_VOSR_RANGERDY)
+        {
+          break;
+        }
+    }
 
-  modifyreg32(STM32_PWR_VOSR, PWR_VOSR_R2EN, PWR_VOSR_R1EN);
-  while ((getreg32(STM32_PWR_VOSR) &
-          (PWR_VOSR_R1RDY | PWR_VOSR_R2RDY)) != PWR_VOSR_R1RDY)
+  if (timeout == 0)
     {
+      return;
     }
 
-  /* Three wait states are required before raising HCLK to 96 MHz. */
+  /* Configure FLASH before raising HCLK. */
 
   modifyreg32(STM32_FLASH_ACR, FLASH_ACR_LATENCY_MASK,
-              FLASH_ACR_LATENCY(3));
+              STM32_FLASH_ACR_LATENCY);
 
-  /* Select MSIRC0 divided by one and use it as the 96 MHz system clock. */
+  /* Configure and start MSIS. */
 
   regval  = getreg32(STM32_RCC_ICSCR1);
   regval &= ~(RCC_ICSCR1_MSISSEL | RCC_ICSCR1_MSISDIV_MASK);
-  regval |= RCC_ICSCR1_MSIRGSEL;
+  regval |= RCC_ICSCR1_MSIRGSEL | STM32_RCC_ICSCR1_MSISSEL |
+            STM32_RCC_ICSCR1_MSISDIV;
   putreg32(regval, STM32_RCC_ICSCR1);
 
   modifyreg32(STM32_RCC_CR, 0, RCC_CR_MSISON);
-  while ((getreg32(STM32_RCC_CR) & RCC_CR_MSISRDY) == 0)
+  for (timeout = CLOCK_READY_TIMEOUT; timeout > 0; timeout--)
     {
+      if ((getreg32(STM32_RCC_CR) & RCC_CR_MSISRDY) != 0)
+        {
+          break;
+        }
     }
 
-  modifyreg32(STM32_RCC_CFGR1, RCC_CFGR1_SW_MASK, RCC_CFGR1_SW_MSIS);
-  while ((getreg32(STM32_RCC_CFGR1) & RCC_CFGR1_SWS_MASK) !=
-         RCC_CFGR1_SWS_MSIS)
+  if (timeout == 0)
     {
+      return;
     }
 
-  /* Keep all bus clocks undivided. */
+  /* Configure the AHB and APB prescalers. */
 
   modifyreg32(STM32_RCC_CFGR2,
               RCC_CFGR2_HPRE_MASK | RCC_CFGR2_PPRE1_MASK |
-              RCC_CFGR2_PPRE2_MASK, 0);
-  modifyreg32(STM32_RCC_CFGR3, RCC_CFGR3_PPRE3_MASK, 0);
+              RCC_CFGR2_PPRE2_MASK,
+              STM32_RCC_CFGR2_HPRE | STM32_RCC_CFGR2_PPRE1 |
+              STM32_RCC_CFGR2_PPRE2);
+  modifyreg32(STM32_RCC_CFGR3, RCC_CFGR3_PPRE3_MASK,
+              STM32_RCC_CFGR3_PPRE3);
+
+  /* Use MSIS as the system clock and wait for the switch to complete. */
+
+  modifyreg32(STM32_RCC_CFGR1, RCC_CFGR1_SW_MASK, RCC_CFGR1_SW_MSIS);
+  for (timeout = CLOCK_READY_TIMEOUT; timeout > 0; timeout--)
+    {
+      if ((getreg32(STM32_RCC_CFGR1) & RCC_CFGR1_SWS_MASK) ==
+          RCC_CFGR1_SWS_MSIS)
+        {
+          break;
+        }
+    }
 }
+#endif
 
 /****************************************************************************
  * Name: stm32_rcc_enableperipherals

boards/Kconfig

@@ -3311,6 +3311,14 @@ config ARCH_BOARD_NUCLEO_U5A5ZJ_Q
 		MCU. The STM32U5A5 is a Cortex-M33 optimised for low-power operation
 		at up to 160MHz operation with 4MB Flash memory and 2.5MB SRAM.
 
+config ARCH_BOARD_NUCLEO_U3C5ZI_Q
+	bool "STMicro NUCLEO-U3C5ZI-Q board"
+	depends on ARCH_CHIP_STM32U3C5ZI
+	---help---
+		STMicro NUCLEO-U3C5ZI-Q development board featuring the STM32U3C5ZI,
+		a Cortex-M33 MCU running at up to 96 MHz with 2 MiB Flash and
+		640 KiB SRAM.
+
 config ARCH_BOARD_STM32L476VG_DISCO
 	bool "STMicro STM32L476VG -Discovery board"
 	depends on ARCH_CHIP_STM32L476RG
@@ -4176,6 +4184,7 @@ config ARCH_BOARD
 	default "nucleo-h563zi"                if ARCH_BOARD_NUCLEO_H563ZI
 	default "nucleo-n657x0-q"              if ARCH_BOARD_NUCLEO_N657X0_Q
 	default "nucleo-u5a5zj-q"              if ARCH_BOARD_NUCLEO_U5A5ZJ_Q
+	default "nucleo-u3c5zi-q"              if ARCH_BOARD_NUCLEO_U3C5ZI_Q
 	default "stm32l476vg-disco"            if ARCH_BOARD_STM32L476VG_DISCO
 	default "stm32l476-mdk"                if ARCH_BOARD_STM32L476_MDK
 	default "stm32l4r9ai-disco"            if ARCH_BOARD_STM32L4R9AI_DISCO
@@ -4835,6 +4844,9 @@ endif
 if ARCH_BOARD_NUCLEO_U5A5ZJ_Q
 source "boards/arm/stm32u5/nucleo-u5a5zj-q/Kconfig"
 endif
+if ARCH_BOARD_NUCLEO_U3C5ZI_Q
+source "boards/arm/stm32u3/nucleo-u3c5zi-q/Kconfig"
+endif
 if ARCH_BOARD_NUCLEO_L432KC
 source "boards/arm/stm32l4/nucleo-l432kc/Kconfig"
 endif
@@ -5460,7 +5472,7 @@ endif
 if ARCH_CHIP_SAMV7
 source "boards/arm/samv7/common/Kconfig"
 endif
-if ARCH_CHIP_STM32C0 || ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32L1 || ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32L5 || ARCH_CHIP_STM32U0 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB || ARCH_CHIP_STM32WL5 || ARCH_CHIP_STM32N6
+if ARCH_CHIP_STM32C0 || ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32L1 || ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32L5 || ARCH_CHIP_STM32U0 || ARCH_CHIP_STM32U3 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB || ARCH_CHIP_STM32WL5 || ARCH_CHIP_STM32N6
 source "boards/arm/common/stm32/Kconfig"
 endif
 if ARCH_CHIP_RP2040

boards/arm/stm32u3/common/CMakeLists.txt

@@ -0,0 +1,25 @@
+# ##############################################################################
+# boards/arm/stm32u3/common/CMakeLists.txt
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more contributor
+# license agreements.  See the NOTICE file distributed with this work for
+# additional information regarding copyright ownership.  The ASF licenses this
+# file to you under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License.  You may obtain a copy of
+# the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations under
+# the License.
+#
+# ##############################################################################
+
+if(CONFIG_ARCH_BOARD_COMMON)
+  add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common)
+endif()

boards/arm/stm32u3/common/Makefile

@@ -0,0 +1,38 @@
+#############################################################################
+# boards/arm/stm32u3/common/Makefile
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements.  See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership.  The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+#############################################################################
+
+include $(TOPDIR)/Make.defs
+
+STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32
+STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32
+
+include board/Make.defs
+include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs
+
+DEPPATH += --dep-path board
+
+include $(TOPDIR)/boards/Board.mk
+
+ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
+BOARDDIR = $(ARCHSRCDIR)$(DELIM)board
+CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include
+CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR)

boards/arm/stm32u3/nucleo-u3c5zi-q/CMakeLists.txt

@@ -0,0 +1,23 @@
+# ##############################################################################
+# boards/arm/stm32u3/nucleo-u3c5zi-q/CMakeLists.txt
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more contributor
+# license agreements.  See the NOTICE file distributed with this work for
+# additional information regarding copyright ownership.  The ASF licenses this
+# file to you under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License.  You may obtain a copy of
+# the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations under
+# the License.
+#
+# ##############################################################################
+
+add_subdirectory(src)

boards/arm/stm32u3/nucleo-u3c5zi-q/Kconfig

@@ -0,0 +1,8 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_BOARD_NUCLEO_U3C5ZI_Q
+
+endif