arch/arm/stm32h5: Add WWDG support.

Add WWDG driver support for STM32H5.
Enable the WWDG peripheral clock when WWDG is enabled.

It's based on STM32H7. This contribution has been
reduced to the minimum number of changes from the
H7 version.

Signed-off-by: Liam Howatt <liamhowatt@geotab.com>
Co-authored-by: Liam Howatt <liamhowatt@geotab.com>

Author: 2 people

arch/arm/src/stm32h5/Make.defs

@@ -120,6 +120,10 @@ ifeq ($(CONFIG_STM32_IWDG),y)
 CHIP_CSRCS += stm32_iwdg.c
 endif
 
+ifeq ($(CONFIG_STM32_WWDG),y)
+CHIP_CSRCS += stm32_wwdg.c
+endif
+
 # Required chip type specific files
 
 ifeq ($(CONFIG_STM32_STM32H5XXXX),y)

arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h

@@ -642,9 +642,10 @@
 #define RCC_APB1LENR_TIM5EN            (1 << 3)  /* Bit 3:  TIM5 clock enable */
 #define RCC_APB1LENR_TIM6EN            (1 << 4)  /* Bit 4:  TIM6 clock enable */
 #define RCC_APB1LENR_TIM7EN            (1 << 5)  /* Bit 5:  TIM7 clock enable */
-#define RCC_APB1LENR_TIM12EN           (1 << 6)  /* Bit 5:  TIM12 clock enable */
-#define RCC_APB1LENR_TIM13EN           (1 << 7)  /* Bit 5:  TIM13 clock enable */
-#define RCC_APB1LENR_TIM14EN           (1 << 8)  /* Bit 5:  TIM14 clock enable */
+#define RCC_APB1LENR_TIM12EN           (1 << 6)  /* Bit 6:  TIM12 clock enable */
+#define RCC_APB1LENR_TIM13EN           (1 << 7)  /* Bit 7:  TIM13 clock enable */
+#define RCC_APB1LENR_TIM14EN           (1 << 8)  /* Bit 8:  TIM14 clock enable */
+#define RCC_APB1LENR_WWDGEN            (1 << 11) /* Bit 11: WWDG clock enable */
 #define RCC_APB1LENR_SPI2EN            (1 << 14) /* Bit 14: SPI2 clock enable */
 #define RCC_APB1LENR_SPI3EN            (1 << 15) /* Bit 15: SPI3 clock enable */
 #define RCC_APB1LENR_USART2EN          (1 << 17) /* Bit 17: USART2 clock enable */