Collaboration request: hardware, HDL, CODAC/EPICS, and runtime deployment evidence

[anulum]

Blocked modules

• src/scpn_control/scpn/fpga_export.py
• src/scpn_control/phase/kuramoto.py
• src/scpn_control
• src/scpn_control/core/checkpoint.py

Needed evidence

• Generated HDL run through real Vivado, Quartus, or Yosys synthesis.
• Resource utilisation, timing closure, and bit-accurate simulator evidence for supported target families.
• Published Kuramoto-Sakaguchi benchmark cases for synchronisation/stability metrics.
• Rust/Python parity evidence and timestep-convergence checks for deployment-target oscillator counts.
• Hardware-target or replay-fixture evidence for future phase, spiking, and replay runtime markers.
• Checkpoint schema versioning and migration fixtures before long-running production campaigns depend on replay compatibility.
• CODAC/EPICS timing, interlock behaviour, backpressure, HIL replay, and deployment-target runtime evidence where applicable.

Claim unblocked

Hardware-readiness, runtime-deployment, and long-campaign replay compatibility claims. Until then, these remain bounded runtime/export contracts.