diff --git a/drivers/clk/adi/clk-adi-sc846.c b/drivers/clk/adi/clk-adi-sc846.c index 05976699997a..eb4b952adf08 100644 --- a/drivers/clk/adi/clk-adi-sc846.c +++ b/drivers/clk/adi/clk-adi-sc846.c @@ -1,12 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * (C) Copyright 2022 - Analog Devices, Inc. + * Clock support for ADI SC846 processor * - * Written and/or maintained by Timesys Corporation - * - * Author: Greg Malysa - * - * Ported from Linux: Nathan Barrett-Morrison + * (C) Copyright 2026 - Analog Devices, Inc. */ #include @@ -66,8 +62,13 @@ static int sc846_clock_probe(struct udevice *dev) cdu = devm_ioremap(dev, res.start, resource_size(&res)); /* Input clock configuration */ - clk_get_by_name(dev, "dummy", &dummy); - clk_get_by_name(dev, "sys_clkin0", &clkin0); + ret = clk_get_by_name(dev, "dummy", &dummy); + if (ret < 0) + return ret; + + ret = clk_get_by_name(dev, "sys_clkin0", &clkin0); + if (ret < 0) + return ret; clks[ADSP_SC846_CLK_DUMMY] = &dummy; clks[ADSP_SC846_CLK_SYS_CLKIN0] = &clkin0; @@ -93,28 +94,33 @@ static int sc846_clock_probe(struct udevice *dev) clks[ADSP_SC846_CLK_CGU0_PLLCLK] = clk_register_fixed_factor(NULL, "cgu0_pllclk", "cgu0_vco", CLK_SET_RATE_PARENT, - 1, 4); + 1, 2); clks[ADSP_SC846_CLK_CGU1_PLLCLK] = clk_register_fixed_factor(NULL, "cgu1_pllclk", "cgu1_vco", CLK_SET_RATE_PARENT, - 1, 4); - + 1, 2); + clks[ADSP_SC846_CLK_CGU0_PLLCLK_HALF] = + clk_register_fixed_factor(NULL, "cgu0_pllclk_half", "cgu0_pllclk", + CLK_SET_RATE_PARENT, 1, 2); + clks[ADSP_SC846_CLK_CGU1_PLLCLK_HALF] = + clk_register_fixed_factor(NULL, "cgu1_pllclk_half", "cgu1_pllclk", + CLK_SET_RATE_PARENT, 1, 2); /* CGU0 DIV */ /* Dividers from pll output */ - clks[ADSP_SC846_CLK_CGU0_CDIV] = cgu_divider("cgu0_cdiv", "cgu0_pllclk", + clks[ADSP_SC846_CLK_CGU0_CDIV] = cgu_divider("cgu0_cdiv", "cgu0_pllclk_half", cgu0 + CGU_DIV, 0, 5, 0); - clks[ADSP_SC846_CLK_CGU0_SYSCLK] = cgu_divider("sysclk_0", "cgu0_pllclk", + clks[ADSP_SC846_CLK_CGU0_SYSCLK] = cgu_divider("sysclk_0", "cgu0_pllclk_half", cgu0 + CGU_DIV, 8, 5, 0); - clks[ADSP_SC846_CLK_CGU0_DDIV] = cgu_divider("cgu0_ddiv", "cgu0_pllclk", + clks[ADSP_SC846_CLK_CGU0_DDIV] = cgu_divider("cgu0_ddiv", "cgu0_pllclk_half", cgu0 + CGU_DIV, 16, 5, 0); - clks[ADSP_SC846_CLK_CGU0_ODIV] = cgu_divider("cgu0_odiv", "cgu0_pllclk", + clks[ADSP_SC846_CLK_CGU0_ODIV] = cgu_divider("cgu0_odiv", "cgu0_pllclk_half", cgu0 + CGU_DIV, 22, 7, 0); clks[ADSP_SC846_CLK_CGU0_S0SELDIV] = cgu_divider("cgu0_s0seldiv", "sysclk_0", cgu0 + CGU_DIV, 5, 3, 0); clks[ADSP_SC846_CLK_CGU0_S1SELDIV] = cgu_divider("cgu0_s1seldiv", "sysclk_0", cgu0 + CGU_DIV, 13, 3, 0); clks[ADSP_SC846_CLK_CGU0_S1SELEXDIV] = cgu_divider("cgu0_s1selexdiv", - "cgu0_pllclk", + "cgu0_pllclk_half", cgu0 + CGU_DIVEX, 16, 8, 0); clks[ADSP_SC846_CLK_CGU0_S1SEL] = clk_register_mux(NULL, "cgu0_sclk1sel", cgu0_s1sels, 2, @@ -126,10 +132,6 @@ static int sc846_clock_probe(struct udevice *dev) "cgu0_vco", CLK_SET_RATE_PARENT, 1, 3); - clks[ADSP_SC846_CLK_CGU0_CCLK2_1] = clk_register_fixed_factor(NULL, "cclk2_1", - "cgu0_vco", - CLK_SET_RATE_PARENT, - 1, 3); /* DCLK1_x = VCO/5 */ clks[ADSP_SC846_CLK_CGU0_DCLK1_0] = clk_register_fixed_factor(NULL, "dclk1_0", "cgu0_vco", @@ -137,23 +139,23 @@ static int sc846_clock_probe(struct udevice *dev) 1, 5); /* CGU1 DIV */ - clks[ADSP_SC846_CLK_CGU1_CDIV] = cgu_divider("cgu1_cdiv", "cgu1_pllclk", + clks[ADSP_SC846_CLK_CGU1_CDIV] = cgu_divider("cgu1_cdiv", "cgu1_pllclk_half", cgu1 + CGU_DIV, 0, 5, 0); - clks[ADSP_SC846_CLK_CGU1_SYSCLK] = cgu_divider("sysclk_1", "cgu1_pllclk", + clks[ADSP_SC846_CLK_CGU1_SYSCLK] = cgu_divider("sysclk_1", "cgu1_pllclk_half", cgu1 + CGU_DIV, 8, 5, 0); - clks[ADSP_SC846_CLK_CGU1_DDIV] = cgu_divider("cgu1_ddiv", "cgu1_pllclk", + clks[ADSP_SC846_CLK_CGU1_DDIV] = cgu_divider("cgu1_ddiv", "cgu1_pllclk_half", cgu1 + CGU_DIV, 16, 5, 0); - clks[ADSP_SC846_CLK_CGU1_ODIV] = cgu_divider("cgu1_odiv", "cgu1_pllclk", + clks[ADSP_SC846_CLK_CGU1_ODIV] = cgu_divider("cgu1_odiv", "cgu1_pllclk_half", cgu1 + CGU_DIV, 22, 7, 0); clks[ADSP_SC846_CLK_CGU1_S0SELDIV] = cgu_divider("cgu1_s0seldiv", "sysclk_1", cgu1 + CGU_DIV, 5, 3, 0); clks[ADSP_SC846_CLK_CGU1_S1SELDIV] = cgu_divider("cgu1_s1seldiv", "sysclk_1", cgu1 + CGU_DIV, 13, 3, 0); clks[ADSP_SC846_CLK_CGU1_S0SELEXDIV] = cgu_divider("cgu1_s0selexdiv", - "cgu1_pllclk", + "cgu1_pllclk_half", cgu1 + CGU_DIVEX, 0, 8, 0); clks[ADSP_SC846_CLK_CGU1_S1SELEXDIV] = cgu_divider("cgu1_s1selexdiv", - "cgu1_pllclk", + "cgu1_pllclk_half", cgu1 + CGU_DIVEX, 16, 8, 0); clks[ADSP_SC846_CLK_CGU1_S0SEL] = clk_register_mux(NULL, "cgu1_sclk0sel", cgu1_s0sels, 2, @@ -167,6 +169,9 @@ static int sc846_clock_probe(struct udevice *dev) "cgu1_vco", CLK_SET_RATE_PARENT, 1, 3); + clks[ADSP_SC846_CLK_CGU1_DCLK1_1] = + clk_register_fixed_factor(NULL, "dclk1_1", "cgu1_vco", + CLK_SET_RATE_PARENT, 1, 5); /* Gates to enable CGU outputs */ clks[ADSP_SC846_CLK_CGU0_CCLK0] = cgu_gate("cclk0_0", "cgu0_cdiv", diff --git a/include/dt-bindings/clock/adi-sc5xx-clock.h b/include/dt-bindings/clock/adi-sc5xx-clock.h index 261bb6f9c9f2..4462a474329b 100644 --- a/include/dt-bindings/clock/adi-sc5xx-clock.h +++ b/include/dt-bindings/clock/adi-sc5xx-clock.h @@ -38,48 +38,50 @@ #define ADSP_SC846_CLK_CGU1_S0SEL 24 #define ADSP_SC846_CLK_CGU1_S1SEL 25 #define ADSP_SC846_CLK_CGU0_CCLK2_0 26 -#define ADSP_SC846_CLK_CGU0_CCLK2_1 27 -#define ADSP_SC846_CLK_CGU0_DCLK1_0 28 -#define ADSP_SC846_CLK_CGU0_CCLK0 29 -#define ADSP_SC846_CLK_CGU0_OCLK 30 -#define ADSP_SC846_CLK_CGU0_DCLK 31 -#define ADSP_SC846_CLK_CGU0_SCLK1 32 -#define ADSP_SC846_CLK_CGU0_SCLK0 33 -#define ADSP_SC846_CLK_CGU1_CCLK0 34 -#define ADSP_SC846_CLK_CGU1_OCLK 35 -#define ADSP_SC846_CLK_CGU1_DCLK 36 -#define ADSP_SC846_CLK_CGU1_SCLK1 37 -#define ADSP_SC846_CLK_CGU1_SCLK0 38 -#define ADSP_SC846_CLK_CGU1_CCLK2 39 -#define ADSP_SC846_CLK_SHARC0_SEL 40 -#define ADSP_SC846_CLK_ARM0_SEL 41 -#define ADSP_SC846_CLK_ARM1_SEL 42 -#define ADSP_SC846_CLK_CDU_DDR_SEL 43 -#define ADSP_SC846_CLK_CAN_SEL 44 -#define ADSP_SC846_CLK_SPDIF_SEL 45 -#define ADSP_SC846_CLK_SPI_SEL 46 -#define ADSP_SC846_CLK_GIGE_SEL 47 -#define ADSP_SC846_CLK_XSPI2_SEL 48 -#define ADSP_SC846_CLK_LP_SEL 49 -#define ADSP_SC846_CLK_XSPI_SEL 50 -#define ADSP_SC846_CLK_TRACE_SEL 51 -#define ADSP_SC846_CLK_PWM_SEL 52 -#define ADSP_SC846_CLK_MSHC_SEL 53 -#define ADSP_SC846_CLK_SHARC0 54 -#define ADSP_SC846_CLK_ARM0 55 -#define ADSP_SC846_CLK_ARM1 56 -#define ADSP_SC846_CLK_CDU_DDR 57 -#define ADSP_SC846_CLK_CAN 58 -#define ADSP_SC846_CLK_SPDIF 59 -#define ADSP_SC846_CLK_SPI 60 -#define ADSP_SC846_CLK_GIGE 61 -#define ADSP_SC846_CLK_XSPI2 62 -#define ADSP_SC846_CLK_LP 63 -#define ADSP_SC846_CLK_XSPI 64 -#define ADSP_SC846_CLK_TRACE 65 -#define ADSP_SC846_CLK_PWM 66 -#define ADSP_SC846_CLK_MSHC 67 -#define ADSP_SC846_CLK_END 68 +#define ADSP_SC846_CLK_CGU0_DCLK1_0 27 +#define ADSP_SC846_CLK_CGU0_CCLK0 28 +#define ADSP_SC846_CLK_CGU0_OCLK 29 +#define ADSP_SC846_CLK_CGU0_DCLK 30 +#define ADSP_SC846_CLK_CGU0_SCLK1 31 +#define ADSP_SC846_CLK_CGU0_SCLK0 32 +#define ADSP_SC846_CLK_CGU1_CCLK0 33 +#define ADSP_SC846_CLK_CGU1_OCLK 34 +#define ADSP_SC846_CLK_CGU1_DCLK 35 +#define ADSP_SC846_CLK_CGU1_SCLK1 36 +#define ADSP_SC846_CLK_CGU1_SCLK0 37 +#define ADSP_SC846_CLK_CGU1_CCLK2 38 +#define ADSP_SC846_CLK_SHARC0_SEL 39 +#define ADSP_SC846_CLK_ARM0_SEL 40 +#define ADSP_SC846_CLK_ARM1_SEL 41 +#define ADSP_SC846_CLK_CDU_DDR_SEL 42 +#define ADSP_SC846_CLK_CAN_SEL 43 +#define ADSP_SC846_CLK_SPDIF_SEL 44 +#define ADSP_SC846_CLK_SPI_SEL 45 +#define ADSP_SC846_CLK_GIGE_SEL 46 +#define ADSP_SC846_CLK_XSPI2_SEL 47 +#define ADSP_SC846_CLK_LP_SEL 48 +#define ADSP_SC846_CLK_XSPI_SEL 49 +#define ADSP_SC846_CLK_TRACE_SEL 50 +#define ADSP_SC846_CLK_PWM_SEL 51 +#define ADSP_SC846_CLK_MSHC_SEL 52 +#define ADSP_SC846_CLK_SHARC0 53 +#define ADSP_SC846_CLK_ARM0 54 +#define ADSP_SC846_CLK_ARM1 55 +#define ADSP_SC846_CLK_CDU_DDR 56 +#define ADSP_SC846_CLK_CAN 57 +#define ADSP_SC846_CLK_SPDIF 58 +#define ADSP_SC846_CLK_SPI 59 +#define ADSP_SC846_CLK_GIGE 60 +#define ADSP_SC846_CLK_XSPI2 61 +#define ADSP_SC846_CLK_LP 62 +#define ADSP_SC846_CLK_XSPI 63 +#define ADSP_SC846_CLK_TRACE 64 +#define ADSP_SC846_CLK_PWM 65 +#define ADSP_SC846_CLK_MSHC 66 +#define ADSP_SC846_CLK_CGU0_PLLCLK_HALF 67 +#define ADSP_SC846_CLK_CGU1_PLLCLK_HALF 68 +#define ADSP_SC846_CLK_CGU1_DCLK1_1 69 +#define ADSP_SC846_CLK_END 70 //ADSP-SC594 #define ADSP_SC594_CLK_DUMMY 0