From 719bf69842861b78e114abace0beb8f14852d2a7 Mon Sep 17 00:00:00 2001 From: mandrica Date: Thu, 6 Aug 2026 12:21:09 +0300 Subject: [PATCH] reference-designs/pulsar-lvds-adc: Add documentation pages Signed-off-by: mandrica --- .../pulsar-lvds-adc/index.rst | 150 ++++++++++++++ .../pulsar-lvds-adc/prerequisites.rst | 65 ++++++ .../pulsar-lvds-adc/quickstart/index.rst | 73 +++++++ .../pulsar-lvds-adc/quickstart/zed.rst | 196 ++++++++++++++++++ .../pulsar-lvds-adc/user-guide.rst | 193 +++++++++++++++++ 5 files changed, 677 insertions(+) create mode 100644 docs/solutions/reference-designs/pulsar-lvds-adc/index.rst create mode 100644 docs/solutions/reference-designs/pulsar-lvds-adc/prerequisites.rst create mode 100644 docs/solutions/reference-designs/pulsar-lvds-adc/quickstart/index.rst create mode 100644 docs/solutions/reference-designs/pulsar-lvds-adc/quickstart/zed.rst create mode 100644 docs/solutions/reference-designs/pulsar-lvds-adc/user-guide.rst diff --git a/docs/solutions/reference-designs/pulsar-lvds-adc/index.rst b/docs/solutions/reference-designs/pulsar-lvds-adc/index.rst new file mode 100644 index 0000000000..e589fa8eed --- /dev/null +++ b/docs/solutions/reference-designs/pulsar-lvds-adc/index.rst @@ -0,0 +1,150 @@ +.. _pulsar-lvds-adc: + +PULSAR-LVDS-ADC +=============== + +16-Bit/18-Bit, 5 MSPS to 10 MSPS PulSAR LVDS Differential ADC Family + +.. + To be added: chip or evaluation board photo, download from ADI product page + (e.g. AD7960) and save as images/pulsar_lvds_adc_chip.png, then uncomment: + .. image:: images/pulsar_lvds_adc_chip.png + :align: left + :width: 100 + +Overview +-------- + +The :adi:`AD7625`, :adi:`AD7626`, :adi:`AD7960`, and :adi:`AD7961` are +high-performance successive approximation register (SAR) analog-to-digital +converters from the PulSAR LVDS family. They feature charge redistribution +SAR architecture with LVDS self-clocked or echoed-clock serial interfaces. + +The :adi:`AD7625` is a 16-bit, 6 MSPS ADC and the :adi:`AD7626` is a 16-bit, +10 MSPS ADC. Both achieve 92 dB SNR with excellent linearity of ±1 LSB INL. +They require an external 2.048 V reference. + +The :adi:`AD7960` is an 18-bit, 5 MSPS ADC and the :adi:`AD7961` is a 16-bit, +5 MSPS ADC. They provide 99 dB SNR (AD7960) and 92 dB SNR (AD7961) with +±1 LSB INL. They operate with an external 5 V reference. + +All devices feature internal reference buffers, low power dissipation, and LVDS +digital outputs suitable for high-speed data acquisition systems. + +Features: + +- 16-bit or 18-bit resolution, up to 10 MSPS throughput +- 92 dB to 99 dB SNR, ±1 LSB INL +- LVDS self-clocked or echoed-clock serial interface +- Internal reference buffer +- Low power dissipation +- Charge redistribution SAR architecture + +Applications: + +- Digital imaging +- High-speed data acquisition +- Telecommunications +- Spectrum analysis +- Test and measurement equipment +- Medical instrumentation + +.. + To be added: evaluation board photo + .. figure:: images/pulsar_lvds_adc_eval.png + :align: center + :width: 400 + + PULSAR-LVDS-ADC evaluation board + +Recommendations +--------------- + +People who follow the flow that is outlined, have a much better experience +with things. However, like many things, documentation is never as complete +as it should be. If you have any questions, feel free to ask on our +:ref:`EngineerZone forums `, but before that, please make +sure you read our documentation thoroughly. + +To better understand these devices, we recommend using one of the following +evaluation boards: + +- :adi:`EVAL-AD7625` for the AD7625 +- :adi:`EVAL-AD7626` for the AD7626 +- :adi:`EVAL-AD7960` for the AD7960 +- :adi:`EVAL-AD7961` for the AD7961 + +Table of contents +----------------- + +#. Using the evaluation board/full stack reference design that we offer: + + #. :ref:`Prerequisites ` - what you + need to get started + #. :ref:`Quick start guides `: + + #. Using the :ref:`Zedboard / Zynq-7000 SoC + ` + + #. Configure an SD Card with + :external+kuiper:doc:`Kuiper ` + + #. Linux Applications + + #. :ref:`iio-oscilloscope` + +#. Design with the AD7625/AD7626/AD7960/AD7961 + + #. HDL reference design + + #. :external+hdl:ref:`pulsar_lvds_adc` which + you must use in your FPGA. + +#. :ref:`Help and Support ` + +Functional Block Diagram +~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. + To be added: functional block diagram + .. figure:: images/pulsar_lvds_adc_block_diagram.png + :width: 1000 + + PULSAR-LVDS-ADC functional block diagram + +.. toctree:: + :hidden: + + user-guide + quickstart/index + prerequisites + +Additional Information and Useful Links +---------------------------------------- + +- :adi:`AD7625 Product Page ` +- :adi:`AD7626 Product Page ` +- :adi:`AD7960 Product Page ` +- :adi:`AD7961 Product Page ` +- :adi:`EVAL-AD7625 Evaluation Board ` +- :adi:`EVAL-AD7626 Evaluation Board ` +- :adi:`EVAL-AD7960 Evaluation Board ` +- :adi:`EVAL-AD7961 Evaluation Board ` +- :adi:`AD7625/AD7626 Data Sheet + ` +- :adi:`AD7960/AD7961 Data Sheet + ` +- :adi:`UG-745: EVAL-AD7625/EVAL-AD7626 User Guide + ` +- :adi:`UG-490: EVAL-AD7960/EVAL-AD7961 User Guide + ` + +Warning +-------- + +.. esd-warning:: + +Help and support +---------------- + +Please go to :ref:`Help and Support ` page. diff --git a/docs/solutions/reference-designs/pulsar-lvds-adc/prerequisites.rst b/docs/solutions/reference-designs/pulsar-lvds-adc/prerequisites.rst new file mode 100644 index 0000000000..d02bd19013 --- /dev/null +++ b/docs/solutions/reference-designs/pulsar-lvds-adc/prerequisites.rst @@ -0,0 +1,65 @@ +.. _pulsar-lvds-adc prerequisites: + +Prerequisites +============= + +What you need, depends on what you are trying to do. As a minimum, you need to +start out with: + +Hardware prerequisites +---------------------- + +#. One of the PulSAR LVDS ADC evaluation boards: + + - :adi:`EVAL-AD7625` (16-bit, 6 MSPS) + - :adi:`EVAL-AD7626` (16-bit, 10 MSPS) + - :adi:`EVAL-AD7960` (18-bit, 5 MSPS) + - :adi:`EVAL-AD7961` (16-bit, 5 MSPS) + +#. An FPGA carrier platform. Our recommended ones can be found + :ref:`here `. + + - There are a few more boards, which do work, but are currently not + supported by us. The experience with the fabric-only solutions is very + close to the ARM/FPGA SoC based solutions, but the GUI runs on a host PC + (Windows or Linux). + +#. Some way to interact with the FPGA platform: + + #. for the ARM/FPGA SoC platforms, this normally includes: + + - Micro-USB cable for UART console + - LAN cable (Ethernet) for SSH or IIO applications + - HDMI or DisplayPort monitor (Optional) + - USB Keyboard (Optional) + - USB Mouse (Optional) + + #. for the FPGA only solutions, this includes: + + - LAN cable (Ethernet) + - Host PC (Windows or Linux) + - Micro-USB cable for UART + - Micro-USB cable for JTAG (PROG) + +#. Internet connection (without proxies makes things much easier) to update + the scripts/binaries on the SD card that came with the ADI FMC Card + (firewalls are OK, proxies make things a pain). +#. Test equipment for generating analog input signals. +#. An SD card with at least 16GB of memory (in case you're using Linux). You + should have received one when purchasing the evaluation board. + +Software prerequisites +---------------------- + +Normally, for basic functionalities regarding visualizing the data received +from the FPGA, we use the following: + +#. :external+scopy:doc:`Scopy ` v2.0 or later (must contain the IIO + plugin) +#. :git-iio-oscilloscope:`IIO Oscilloscope ` +#. UART terminal application (PuTTY/TeraTerm/Minicom/MobaXterm), 115200, 8N1 + +.. note:: + + :adi:`ADI <>` does not offer FPGA carrier platforms for sale or loan; + getting one yourself is the normal part of development or evaluation. diff --git a/docs/solutions/reference-designs/pulsar-lvds-adc/quickstart/index.rst b/docs/solutions/reference-designs/pulsar-lvds-adc/quickstart/index.rst new file mode 100644 index 0000000000..6bd0e2a67c --- /dev/null +++ b/docs/solutions/reference-designs/pulsar-lvds-adc/quickstart/index.rst @@ -0,0 +1,73 @@ +.. _pulsar-lvds-adc quickstart: + +Quickstart +========== + +The Quick start guides provide simple step by step instructions on how to +do an initial system setup for the PulSAR LVDS ADC evaluation boards +(:adi:`EVAL-AD7625`, :adi:`EVAL-AD7626`, :adi:`EVAL-AD7960`, +:adi:`EVAL-AD7961`) on various FPGA development boards. In these guides, we +will discuss how to program the bitstream, run a no-OS program or boot a Linux +distribution. + +.. toctree:: + + Zedboard + +.. _pulsar-lvds-adc carriers: + +Supported carriers +------------------ + +The PulSAR LVDS ADC evaluation boards are, by definition, "FPGA +mezzanine cards" (FMC); that means they need a carrier to plug into. + +The carriers we support are: + +.. list-table:: + :header-rows: 1 + + - - FPGA board + - EVAL-AD7625/AD7626/AD7960/AD7961 + - - `ZedBoard + `__ + - FMC LPC + +Supported Environments +---------------------- + +The supported OS are: + +.. list-table:: + :header-rows: 1 + + - - FPGA board + - HDL + - Linux software + - No-OS software + - - `ZedBoard + `__ + - Yes + - Yes + - Yes + +Hardware Setup +-------------- + +The evaluation board connects to the FMC LPC connector of the carrier board. +The carrier setup requires power, UART (115200), ethernet (Linux), HDMI +(if available) and/or JTAG (no-OS) connections. + +A few typical setups are shown below. + +ZedBoard + PulSAR LVDS ADC +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. + To be added: photo of the PulSAR LVDS ADC evaluation board connected to + the ZedBoard via FMC LPC connector (hardware setup photo) + .. figure:: ../images/pulsar_lvds_adc_zed_setup.jpg + :align: center + :width: 500 + + ZedBoard + PulSAR LVDS ADC hardware setup diff --git a/docs/solutions/reference-designs/pulsar-lvds-adc/quickstart/zed.rst b/docs/solutions/reference-designs/pulsar-lvds-adc/quickstart/zed.rst new file mode 100644 index 0000000000..dee48a0cec --- /dev/null +++ b/docs/solutions/reference-designs/pulsar-lvds-adc/quickstart/zed.rst @@ -0,0 +1,196 @@ +.. _pulsar-lvds-adc quickstart zed: + +ZED Quickstart +============== + +This guide provides quick instructions on how to set up a PulSAR LVDS ADC +evaluation board (:adi:`EVAL-AD7625`, :adi:`EVAL-AD7626`, :adi:`EVAL-AD7960`, +or :adi:`EVAL-AD7961`) on: + +- `ZedBoard + `__ FMC LPC + +.. figure:: ../../images/ZedBoard.png + :align: center + :width: 600 + + ZedBoard development platform + +.. esd-warning:: + +Using Linux as software +----------------------- + +Necessary files +~~~~~~~~~~~~~~~ + +.. note:: + + The SD card includes several folders in the root directory of the BOOT + partition. In order to configure the SD card to work with a specific FPGA + board and ADI hardware, several files must be copied onto the root directory. + Using the host PC, drag and drop the required files onto the BOOT partition, + and use the EJECT function when removing the SD card from the reader. + +The following files are needed for the system to boot: + +- HDL boot image: ``BOOT.BIN`` +- Linux Kernel image: ``uImage`` +- Linux device tree: ``devicetree.dtb`` + +They can either be taken from the SD card -- already generated by us, or you can +build them manually: + +- Instructions on how to choose the boot files from the SD card can be found in + the **Platform-Specific Manual Steps** section from here: + :external+kuiper:ref:`hardware-configuration`. +- Instructions on how to manually build the boot files from source can be found + here: + + - :ref:`linux-kernel zynq` (the only difference compared to the ZynqMP is that + instead of running ``make adi_zynqmp_defconfig``, you must run ``make + zynq_xcomm_adv7511_defconfig``) + - :external+hdl:ref:`pulsar_lvds_adc` build documentation. More HDL build + details at :external+hdl:ref:`build_hdl`. + +.. important:: + + Some projects provide multiple devicetree files in the SD card's boot folders. + Make sure you select the devicetree that matches your specific use case. + + The HDL project supports a build parameter ``RESOLUTION_16_18N`` that must + match your evaluation board: + + - ``RESOLUTION_16_18N=0``: 18-bit mode (for AD7960) + - ``RESOLUTION_16_18N=1``: 16-bit mode (for AD7625, AD7626, AD7961) + +Required Software +~~~~~~~~~~~~~~~~~ + +- SD Card 16GB imaged with :external+kuiper:doc:`Kuiper ` (check out that + guide on how to do it, then come back to this section) +- A UART terminal (Putty/Tera Term/Minicom, etc.) with baud rate 115200 (8N1) + +Required Hardware +~~~~~~~~~~~~~~~~~ + +- AMD Xilinx `ZedBoard + `__ FPGA + board and its power supply (12V) +- One of the PulSAR LVDS ADC evaluation boards: :adi:`EVAL-AD7625`, + :adi:`EVAL-AD7626`, :adi:`EVAL-AD7960`, or :adi:`EVAL-AD7961` +- SD card with at least 16GB of memory +- Micro-USB cable (UART) +- LAN cable (Ethernet) +- Signal generator + +More details as to why you need these can be found at :ref:`pulsar-lvds-adc +prerequisites`. + +Testing +~~~~~~~ + +Creating the setup +^^^^^^^^^^^^^^^^^^ + +In the following example, we will prepare the evaluation setup by connecting +the evaluation board to the ZedBoard and applying a test input signal. + +.. + To be added: photo of the PulSAR LVDS ADC evaluation board connected to + the ZedBoard via FMC LPC connector + +Follow the steps in this order, to avoid damaging the components: + +#. Get the `ZedBoard + `__ + +#. Configure ZedBoard for SD BOOT by placing the jumpers: **JP7** on pins 1-2, + **JP8** on pins 2-3, **JP9** on pins 2-3, **JP10** on pins 1-2 and + **JP11** on pins 1-2. + + .. figure:: ../../images/zed_boot_config_sdcard.jpeg + :width: 400 + + ZedBoard SD boot jumper configuration (JP7-JP11) + + Set the MIO0 jumper (JP6) accordingly. VADJ must be set to **2.5 V** + using the J18 jumper, as specified in the HDL project at + :external+hdl:ref:`pulsar_lvds_adc`. + + .. figure:: ../../eval-ad463x-fmcz/images/zedboard_vadj.jpg + :width: 400 + + ZedBoard VADJ select jumper (J18) set to 2V5 + +#. Insert the SD card into the SD Card Interface Connector (J12) +#. Connect your signal generator to the analog inputs of the evaluation board + using the appropriate SMA connectors or jumper wires. +#. Plug the evaluation board into the FMC LPC Connector (J1) +#. Plug the Power Supply into 12 V Power input connector (J20) (DO NOT turn the + device on). +#. Plug-in an Ethernet cable from your router/switch to the Ethernet port on the + FPGA board +#. Connect the UART port of ZedBoard (J14) to a PC via MicroUSB + + .. figure:: ../../images/zed_pow_eth_uart.jpeg + :width: 600 + + ZedBoard power, Ethernet and UART connections + +#. Turn on the power switch on the FPGA board +#. Observe Kernel and serial console output messages on your terminal + +Boot messages +^^^^^^^^^^^^^ + +.. + To be added: complete boot log from serial console showing U-Boot and + Linux kernel messages for the pulsar_lvds_adc project on ZedBoard + +Using no-OS as software +----------------------- + +The no-OS (bare metal) application for the AD796X family is available in the +:git-no-OS:`Analog Devices no-OS repository <>`. + +Required Software +~~~~~~~~~~~~~~~~~ + +- `Vivado Design Suite `__ +- `Vitis IDE `__ or + `Vitis Classic `__ + +Required Hardware +~~~~~~~~~~~~~~~~~ + +- AMD Xilinx `ZedBoard + `__ FPGA + board and its power supply (12V) +- One of the PulSAR LVDS ADC evaluation boards: :adi:`EVAL-AD7625`, + :adi:`EVAL-AD7626`, :adi:`EVAL-AD7960`, or :adi:`EVAL-AD7961` +- Micro-USB cable (UART) +- Micro-USB cable (JTAG) +- Signal generator + +Testing +~~~~~~~ + +Configure ZedBoard for JTAG boot: + +.. figure:: ../../images/zedboard_no_os_jumpers.jpg + :width: 400 + + ZedBoard JTAG boot jumper configuration + +Connect the JTAG programming cable (Micro-USB) and UART cable (Micro-USB) to +the ZedBoard. Power on the board and program the bitstream using Vivado or +Vitis. + +.. figure:: ../../images/zed_pow_eth_uart_prog.jpeg + :width: 600 + + ZedBoard power, UART and JTAG connections + +.. + To be added: screenshots of no-OS UART output and data capture diff --git a/docs/solutions/reference-designs/pulsar-lvds-adc/user-guide.rst b/docs/solutions/reference-designs/pulsar-lvds-adc/user-guide.rst new file mode 100644 index 0000000000..2690b15227 --- /dev/null +++ b/docs/solutions/reference-designs/pulsar-lvds-adc/user-guide.rst @@ -0,0 +1,193 @@ +.. _pulsar-lvds-adc user-guide: + +User guide +========== + +The complete user guides for the evaluation boards can be found at: + +- :adi:`UG-745: EVAL-AD7625/EVAL-AD7626 User Guide + ` +- :adi:`UG-490: EVAL-AD7960/EVAL-AD7961 User Guide + ` + +Additional documentation: + +- :adi:`AD7625/AD7626 Data Sheet + ` +- :adi:`AD7960/AD7961 Data Sheet + ` + +Hardware guide +-------------- + +Hardware configuration +~~~~~~~~~~~~~~~~~~~~~~ + +The evaluation board connects to the FPGA carrier via the FMC LPC connector. +On the +`ZedBoard `__, +configure the BOOT switches (JP7-JP11) and the MIO0 jumper (JP6) for the +desired boot mode. Refer to the :ref:`pulsar-lvds-adc quickstart zed` guide +for the specific jumper positions for SD card and JTAG boot modes. + +The VADJ voltage provided from the carrier through the FMC connector must be +set to **2.5 V** as specified in the HDL project at +:external+hdl:ref:`pulsar_lvds_adc`. + +The HDL project parameter ``RESOLUTION_16_18N`` controls the ADC resolution +mode: + +- ``RESOLUTION_16_18N=0``: 18-bit mode (for AD7960) +- ``RESOLUTION_16_18N=1``: 16-bit mode (for AD7625, AD7626, AD7961) + +Jumper configuration — AD7625/AD7626 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following jumpers on the EVAL-AD7625/EVAL-AD7626 board must be configured: + +.. list-table:: + :header-rows: 1 + + - - Jumper/Solder link + - Default Position + - Description + - - LK2 + - Inserted + - REFIN to 1.2 V external reference + - - LK3 + - Inserted + - 4.096 V from ADR4540 after AD8031 buffer + - - LK6 + - B + - VCM buffer to amplifier VCM + - - LK9 + - A + - 7 V supply from ADP7102 + - - LK10 + - A + - -2.5 V from ADP2300 + - - JP1, JP2 + - B + - CNV+/CNV- from FPGA + - - JP6 + - B + - 7 V to amplifier +VS + - - JP10 + - B + - -2.5 V to amplifier -VS + - - JP11, JP12 + - B + - ADA4899-1 outputs to ADC inputs + - - JP13, JP14 + - B + - ADA4899-1 outputs to ADC inputs + +Jumper configuration — AD7960/AD7961 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following jumpers on the EVAL-AD7960/EVAL-AD7961 board must be configured: + +.. list-table:: + :header-rows: 1 + + - - Jumper/Solder link + - Default Position + - Description + - - LK2, LK3 + - Inserted + - External amplifier supply options + - - LK4 + - Inserted + - +7 V from ADP7102 + - - LK5 + - B + - -2.5 V from ADP2300 + - - LK6 + - B + - VCM buffer to amplifier VCM + - - LK7 + - B + - +5 V from ADR4550 to REF buffer AD8031 + - - JP1, JP2 + - B + - VIN+/VIN- to ADC driver inputs + - - JP3, JP4 + - B + - ADA4899-1 outputs to AD7960 inputs + - - JP5 + - A + - AD7960 VCM to AD8031 + - - JP7 + - A + - REFIN to 2.048 V external reference + - - JP8 + - B + - +7 V to amplifier +VS + - - JP9 + - B + - -2.5 V to amplifier -VS + +Power supply +~~~~~~~~~~~~ + +The EVAL-AD7625/EVAL-AD7626 boards derive their power from the FMC connector +and internal voltage regulators. Refer to the UG-745 user guide for the +complete power supply schematic. + +The EVAL-AD7960/EVAL-AD7961 boards also derive power from the FMC connector. +The +7 V supply is generated from ADP7102 and -2.5 V from ADP2300. Refer to +the UG-490 user guide for the complete power supply schematic. + +The FPGA carrier board (ZedBoard) is powered separately through its own 12 V +power input connector (J20). + +Analog inputs +~~~~~~~~~~~~~ + +The AD7625/AD7626 are 16-bit differential input ADCs. The AD7960 is an 18-bit +differential input ADC and the AD7961 is a 16-bit differential input ADC. All +devices use charge redistribution SAR architecture. + +For testing purposes, connect a signal generator to the analog inputs of the +evaluation board using the appropriate SMA connectors or jumper wires. For +optimal performance, use a low noise, low distortion signal source. + +Schematic, PCB layout, bill of materials +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Design and layout files for the evaluation boards can be found on the product +pages: + +- :adi:`EVAL-AD7625 design files + ` +- :adi:`EVAL-AD7626 design files + ` +- :adi:`EVAL-AD7960 design files + ` +- :adi:`EVAL-AD7961 design files + ` + +Software guide +-------------- + +The evaluation boards are supported both with Linux (using the Libiio library) +and with no-OS (bare metal). + +Linux +~~~~~ + +The AD796X IIO ADC Linux driver is available in the +:git-linux:`Analog Devices Linux repository <>`. The Libiio library is +cross-platform (Windows, Linux, Mac) with language bindings for C, C#, Python, +and others. Applications that can be used with it are: + +- :git-iio-oscilloscope:`IIO Oscilloscope ` +- :external+scopy:doc:`Scopy ` + +No-OS +~~~~~ + +For no-OS (bare metal), the AD796X driver and project source code are available +in the :git-no-OS:`Analog Devices no-OS repository <>`. Refer to the +:ref:`quickstart guide ` for instructions on +building and running the no-OS application.