create IP from verilog in vivado

[mhanuel26]

Hello Alex,

I found your code, would you please allow me a couple of questions:

1. Can I use this UART Stream AXI to connect with an AXI DMA? The PS is Zynq.

2. If so how can I pack the verilog to use in my vivado project. I am not using Atlys so I would prefer to create a block IP to include in my project.

Will appreciate your comments,

[alexforencich]

Not sure. I think it will probably work, but DMA for a UART seems like a waste of logic resources due to the low bandwidth. Not sure how to properly set things up so you can use it in the Vivado block diagram thing; I avoid that as much as possible unless it's the only way to get things done. It will synthesize fine in Vivado though, there are example designs for Nexys Video and VCU108.

[mhanuel26]

Maybe you are right about the waste of logic resources, I need more than one UART, perhaps three or four, all of them at speeds at least 250K, but 480K desirable. The UART transfers are from an HDLC adapter so it's similar to a stream of bytes always flowing, so I thought DMA might be good solution to simplify software.

I saw the examples, haven't build them but I cannot see in the examples how your AXI UART hook up to the PS, would you then do that in tcl?

[alexforencich]

Oh, I haven't used the zynq chip with a hard core before, so I don't know what the procedure is for connecting that properly. I think it can be done without clunky block diagrams, but I'm not sure how.

Anyway, if the UARTs represent a sufficient amount of bandwidth, then using a DMA core of some sort might be a good idea. However, you might want to find some way of sharing resources so you don't have a whole DMA engine for each UART. I'm not sure the best technique for doing that. I would probably just roll some sort of custom DMA solution that can use the same logic for all of the UARTs. I have also been considering bulding a time-sharing UART that uses the same logic to handle a large number of pins. Haven't had a good chance to implement that, though. The idea is to have a single AXI stream interface that uses TID/TDEST to route bytes to and from each channel. You could then have a DMA engine sitting behind that that has several sets of control registers, corresponding to each UART channel. Not sure offhand the best method for backpressure, though.

[mhanuel26]

Thank you for sharing your thoughts here Alex, which help to visualize more possibilities.
Best,