Skip to content

Verilog 对 >>> 格式化的时候，会变成 >> >(中间多一个空格)，导致编译出错 #70

Open
Open
Verilog 对 >>> 格式化的时候，会变成 >> >(中间多一个空格)，导致编译出错#70

Description

@papillonn
papillonn
opened on May 10, 2021
No description provided.

Metadata

Metadata

Assignees

No one assigned

    Labels

    No labels
    No labels

    Projects

    No projects

    Milestone

    No milestone

    Relationships

    None yet

    Development

    No branches or pull requests

    Issue actions