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# Reading C:/intelFPGA_lite/17.0/modelsim_ase/tcl/vsim/pref.tcl
do bcd_run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 20:35:22 on Mar 10,2020
# vlog -reportprogress 300 ./bcd.sv
# -- Compiling module bcd
# -- Compiling module bcd_tb
#
# Top level modules:
# bcd_tb
# End time: 20:35:23 on Mar 10,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vsim -voptargs=""+acc"" -t 1ps -lib work bcd_testbench
# Start time: 20:35:23 on Mar 10,2020
# ** Error: (vsim-3170) Could not find 'bcd_testbench'.
# Searched libraries:
# D:/OneDrive/Documents/UW/2019-2020/EE371/lab6/work
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./bcd_run.do PAUSED at line 12
do bcd_run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 20:36:03 on Mar 10,2020
# vlog -reportprogress 300 ./bcd.sv
# -- Compiling module bcd
# -- Compiling module bcd_tb
#
# Top level modules:
# bcd_tb
# End time: 20:36:03 on Mar 10,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vsim -voptargs=""+acc"" -t 1ps -lib work bcd_tb
# Start time: 20:35:23 on Mar 10,2020
# Loading sv_std.std
# Loading work.bcd_tb
# Loading work.bcd
# ** Error: Cannot open macro file: bcd_wave.do
# Error in macro ./bcd_run.do line 17
# Cannot open macro file: bcd_wave.do
# while executing
# "do bcd_wave.do"
add wave -position end sim:/bcd_tb/clk
add wave -position end sim:/bcd_tb/reset
add wave -position end sim:/bcd_tb/in
add wave -position end sim:/bcd_tb/out
add wave -position end sim:/bcd_tb/dut/bin
add wave -position end sim:/bcd_tb/dut/ones
add wave -position end sim:/bcd_tb/dut/tens
add wave -position end sim:/bcd_tb/dut/huns
add wave -position end sim:/bcd_tb/dut/thous
add wave -position end sim:/bcd_tb/dut/tenthous
add wave -position end sim:/bcd_tb/dut/done
add wave -position end sim:/bcd_tb/dut/ps
add wave -position end sim:/bcd_tb/dut/ns
run -all
# ** Note: $stop : ./bcd.sv(94)
# Time: 10050 ps Iteration: 1 Instance: /bcd_tb
# Break in Module bcd_tb at ./bcd.sv line 94
write format wave -window .main_pane.wave.interior.cs.body.pw.wf D:/OneDrive/Documents/UW/2019-2020/EE371/lab6/bcd_wave.do
do bcd_run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 20:39:55 on Mar 10,2020
# vlog -reportprogress 300 ./bcd.sv
# -- Compiling module bcd
# -- Compiling module bcd_tb
#
# Top level modules:
# bcd_tb
# End time: 20:39:55 on Mar 10,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# End time: 20:39:59 on Mar 10,2020, Elapsed time: 0:04:36
# Errors: 4, Warnings: 0
# vsim -voptargs=""+acc"" -t 1ps -lib work bcd_tb
# Start time: 20:39:59 on Mar 10,2020
# Loading sv_std.std
# Loading work.bcd_tb
# Loading work.bcd
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body.tree
# ** Note: $stop : ./bcd.sv(94)
# Time: 10050 ps Iteration: 1 Instance: /bcd_tb
# Break in Module bcd_tb at ./bcd.sv line 94
do score_run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 20:54:42 on Mar 10,2020
# vlog -reportprogress 300 ./score.sv
# -- Compiling module score
# -- Compiling module score_tb
#
# Top level modules:
# score_tb
# End time: 20:54:42 on Mar 10,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 20:54:42 on Mar 10,2020
# vlog -reportprogress 300 ./score_disp.sv
# -- Compiling module score_disp
#
# Top level modules:
# score_disp
# End time: 20:54:42 on Mar 10,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 20:54:42 on Mar 10,2020
# vlog -reportprogress 300 ./sprite.sv
# -- Compiling module sprite
# -- Compiling module sprite_tb
#
# Top level modules:
# sprite_tb
# End time: 20:54:42 on Mar 10,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# End time: 20:54:44 on Mar 10,2020, Elapsed time: 0:14:45
# Errors: 0, Warnings: 0
# vsim -voptargs=""+acc"" -t 1ps -lib work score_tb
# Start time: 20:54:44 on Mar 10,2020
# Loading sv_std.std
# Loading work.score_tb
# Loading work.score
# Loading work.bcd
# Loading work.score_disp
# Loading work.sprite
# ** Warning: (vsim-3015) ./score.sv(27): [PCDPC] - Port size (10) does not match connection size (32) for port 'x'. The port definition is at: ./score_disp.sv(3).
# Time: 0 ps Iteration: 0 Instance: /score_tb/dut/ones File: ./score_disp.sv
# ** Warning: (vsim-3015) ./score.sv(28): [PCDPC] - Port size (10) does not match connection size (32) for port 'x'. The port definition is at: ./score_disp.sv(3).
# Time: 0 ps Iteration: 0 Instance: /score_tb/dut/tens File: ./score_disp.sv
# ** Warning: (vsim-3015) ./score.sv(29): [PCDPC] - Port size (10) does not match connection size (32) for port 'x'. The port definition is at: ./score_disp.sv(3).
# Time: 0 ps Iteration: 0 Instance: /score_tb/dut/thous File: ./score_disp.sv
# ** Warning: (vsim-3015) ./score.sv(30): [PCDPC] - Port size (10) does not match connection size (32) for port 'x'. The port definition is at: ./score_disp.sv(3).
# Time: 0 ps Iteration: 0 Instance: /score_tb/dut/tenthous File: ./score_disp.sv
# ** Error: Cannot open macro file: score_wave.do
# Error in macro ./score_run.do line 19
# Cannot open macro file: score_wave.do
# while executing
# "do score_wave.do"
add wave -position end sim:/score_tb/clk
add wave -position end sim:/score_tb/reset
add wave -position end sim:/score_tb/vga_x
add wave -position end sim:/score_tb/vga_y
add wave -position end sim:/score_tb/wave_score
add wave -position end sim:/score_tb/r
add wave -position end sim:/score_tb/g
add wave -position end sim:/score_tb/b
add wave -position end sim:/score_tb/dut/prev_score
add wave -position end sim:/score_tb/dut/total_score
add wave -position end sim:/score_tb/dut/digits
run -all
# ** Note: $stop : ./score.sv(78)
# Time: 10150 ps Iteration: 1 Instance: /score_tb
# Break in Module score_tb at ./score.sv line 78
write format wave -window .main_pane.wave.interior.cs.body.pw.wf D:/OneDrive/Documents/UW/2019-2020/EE371/lab6/scor_wave.do
write format wave -window .main_pane.wave.interior.cs.body.pw.wf D:/OneDrive/Documents/UW/2019-2020/EE371/lab6/score_wave.do
do score_run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 20:57:04 on Mar 10,2020
# vlog -reportprogress 300 ./score.sv
# -- Compiling module score
# -- Compiling module score_tb
#
# Top level modules:
# score_tb
# End time: 20:57:04 on Mar 10,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 20:57:04 on Mar 10,2020
# vlog -reportprogress 300 ./score_disp.sv
# -- Compiling module score_disp
#
# Top level modules:
# score_disp
# End time: 20:57:04 on Mar 10,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 20:57:04 on Mar 10,2020
# vlog -reportprogress 300 ./sprite.sv
# -- Compiling module sprite
# -- Compiling module sprite_tb
#
# Top level modules:
# sprite_tb
# End time: 20:57:04 on Mar 10,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# End time: 20:57:05 on Mar 10,2020, Elapsed time: 0:02:21
# Errors: 3, Warnings: 4
# vsim -voptargs=""+acc"" -t 1ps -lib work score_tb
# Start time: 20:57:05 on Mar 10,2020
# Loading sv_std.std
# Loading work.score_tb
# Loading work.score
# Loading work.bcd
# Loading work.score_disp
# Loading work.sprite
# ** Warning: (vsim-3015) ./score.sv(27): [PCDPC] - Port size (10) does not match connection size (32) for port 'x'. The port definition is at: ./score_disp.sv(3).
# Time: 0 ps Iteration: 0 Instance: /score_tb/dut/ones File: ./score_disp.sv
# ** Warning: (vsim-3015) ./score.sv(28): [PCDPC] - Port size (10) does not match connection size (32) for port 'x'. The port definition is at: ./score_disp.sv(3).
# Time: 0 ps Iteration: 0 Instance: /score_tb/dut/tens File: ./score_disp.sv
# ** Warning: (vsim-3015) ./score.sv(29): [PCDPC] - Port size (10) does not match connection size (32) for port 'x'. The port definition is at: ./score_disp.sv(3).
# Time: 0 ps Iteration: 0 Instance: /score_tb/dut/thous File: ./score_disp.sv
# ** Warning: (vsim-3015) ./score.sv(30): [PCDPC] - Port size (10) does not match connection size (32) for port 'x'. The port definition is at: ./score_disp.sv(3).
# Time: 0 ps Iteration: 0 Instance: /score_tb/dut/tenthous File: ./score_disp.sv
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body.tree
# ** Note: $stop : ./score.sv(77)
# Time: 10150 ps Iteration: 1 Instance: /score_tb
# Break in Module score_tb at ./score.sv line 77
do score_run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 20:59:25 on Mar 10,2020
# vlog -reportprogress 300 ./score.sv
# -- Compiling module score
# -- Compiling module score_tb
#
# Top level modules:
# score_tb
# End time: 20:59:25 on Mar 10,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 20:59:25 on Mar 10,2020
# vlog -reportprogress 300 ./score_disp.sv
# -- Compiling module score_disp
#
# Top level modules:
# score_disp
# End time: 20:59:25 on Mar 10,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 20:59:25 on Mar 10,2020
# vlog -reportprogress 300 ./sprite.sv
# -- Compiling module sprite
# -- Compiling module sprite_tb
#
# Top level modules:
# sprite_tb
# End time: 20:59:26 on Mar 10,2020, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# End time: 20:59:27 on Mar 10,2020, Elapsed time: 0:02:22
# Errors: 0, Warnings: 4
# vsim -voptargs=""+acc"" -t 1ps -lib work score_tb
# Start time: 20:59:27 on Mar 10,2020
# Loading sv_std.std
# Loading work.score_tb
# Loading work.score
# Loading work.bcd
# Loading work.score_disp
# Loading work.sprite
# ** Warning: (vsim-3015) ./score.sv(27): [PCDPC] - Port size (10) does not match connection size (32) for port 'x'. The port definition is at: ./score_disp.sv(3).
# Time: 0 ps Iteration: 0 Instance: /score_tb/dut/ones File: ./score_disp.sv
# ** Warning: (vsim-3015) ./score.sv(28): [PCDPC] - Port size (10) does not match connection size (32) for port 'x'. The port definition is at: ./score_disp.sv(3).
# Time: 0 ps Iteration: 0 Instance: /score_tb/dut/tens File: ./score_disp.sv
# ** Warning: (vsim-3015) ./score.sv(29): [PCDPC] - Port size (10) does not match connection size (32) for port 'x'. The port definition is at: ./score_disp.sv(3).
# Time: 0 ps Iteration: 0 Instance: /score_tb/dut/thous File: ./score_disp.sv
# ** Warning: (vsim-3015) ./score.sv(30): [PCDPC] - Port size (10) does not match connection size (32) for port 'x'. The port definition is at: ./score_disp.sv(3).
# Time: 0 ps Iteration: 0 Instance: /score_tb/dut/tenthous File: ./score_disp.sv
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body.tree
# ** Note: $stop : ./score.sv(77)
# Time: 10150 ps Iteration: 1 Instance: /score_tb
# Break in Module score_tb at ./score.sv line 77
# End time: 00:15:53 on Mar 11,2020, Elapsed time: 3:16:26
# Errors: 0, Warnings: 4