We are currently using combinational memories(single cycle readable ram and rom) which map to LUTs as memory on an FPGA. This is very wasteful, a big memory block must map to a BRAM on FPGA. To make our memory modules mapt o BRAM we have to make them synchronus, which in turn raises another issue, a single cycle cannot wait for load instruction it assumes combinational read.
We will ultimately end up with a pipelined cpu (because of performance e.t.c), so its best that we do it now rather than future.
We are currently using combinational memories(single cycle readable ram and rom) which map to LUTs as memory on an FPGA. This is very wasteful, a big memory block must map to a BRAM on FPGA. To make our memory modules mapt o BRAM we have to make them synchronus, which in turn raises another issue, a single cycle cannot wait for load instruction it assumes combinational read.
We will ultimately end up with a pipelined cpu (because of performance e.t.c), so its best that we do it now rather than future.