We are going to have a 5 stage pipelined rv32i but the system must keep supporting the single cycle rv32i processor with its expected hardware configurations E.g. It will require memories (ram and boot rom) to be combinational (single cycle read/write) but pipelined cpu will expect synchronus memories. So CI must test all hardware not just the latest which is being worked upon.
We are going to have a
5 stage pipelined rv32ibut the system must keep supporting thesingle cycle rv32i processorwith its expected hardware configurations E.g. It will require memories (ram and boot rom) to be combinational (single cycle read/write) but pipelined cpu will expect synchronus memories. So CI must test all hardware not just the latest which is being worked upon.