Verilog-Simple-Risc-Processor/.gitignore at main · VinhTechiee/Verilog-Simple-Risc-Processor · GitHub

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# OS generated files
.DS_Store
.DS_Store?
._*
.Spotlight-V100
.Trashes
ehthumbs.db
Thumbs.db

# LaTeX generated files
_minted
*.lof
*.lot
*.aux
*.bbl
*.blg
*.fls
*.log
*.out
*.toc
*.fdb_latexmk
*.synctex.gz

# Vivado / Xilinx generated files
*.jou
*.str
*.wdb
*.hw
*.sim/
*.ip_user_files/
*.runs/
*.cache/
.Xil/

# Icarus Verilog / GTKWave generated files
*.vvp
*.vcd
*.gtkw

# Test outputs
testbench/output.txt
output.txt

# Editor / IDE settings
.vscode/
.idea/
*.swp
*.bak
*~

# Nix stuffs
.direnv
.envrc
.svlint.toml

# LaTeX auxiliary files
*.synctex
*.synctex_gz
*.synctex.gz

# Verilog simulation outputs
*.out
*.vcd

# LaTeX auxiliary files
*.synctex*