diff --git a/flow/designs/gf12/aes/config.mk b/flow/designs/gf12/aes/config.mk
index 390c800aeb..fa0695bf0f 100644
--- a/flow/designs/gf12/aes/config.mk
+++ b/flow/designs/gf12/aes/config.mk
@@ -6,11 +6,11 @@ export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*
 export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 export ABC_AREA      = 1
 
-export CORE_UTILIZATION  = 40
+export CORE_UTILIZATION  = 45
 export CORE_ASPECT_RATIO = 1
 export CORE_MARGIN       = 2
 
-export PLACE_DENSITY     = 0.80
+export PLACE_DENSITY_LB_ADDON = 0.65
 
 ifeq ($(USE_FILL),1)
 export DESIGN_TYPE = CELL
diff --git a/flow/designs/gf12/aes/constraint.sdc b/flow/designs/gf12/aes/constraint.sdc
index d0a05152d3..f1f2619dcf 100644
--- a/flow/designs/gf12/aes/constraint.sdc
+++ b/flow/designs/gf12/aes/constraint.sdc
@@ -2,7 +2,7 @@ current_design aes_cipher_top
 
 set clk_name clk
 set clk_port_name clk
-set clk_period 420
+set clk_period 360
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/gf12/aes/rules-base.json b/flow/designs/gf12/aes/rules-base.json
index 6995df0560..3ee85f0e28 100644
--- a/flow/designs/gf12/aes/rules-base.json
+++ b/flow/designs/gf12/aes/rules-base.json
@@ -1,4 +1,14 @@
 {
+    "synth__canonical_netlist__hash": {
+        "value": "fb4e74a7b96e9dfc06ab9698f42b0a295610fab0",
+        "compare": "==",
+        "level": "warning"
+    },
+    "synth__netlist__hash": {
+        "value": "8749d894ed2fa7c6ed866a51b10c8b6e7918c96e",
+        "compare": "==",
+        "level": "warning"
+    },
     "synth__design__instance__area__stdcell": {
         "value": 3710.0,
         "compare": "<="
@@ -36,11 +46,11 @@
         "compare": ">="
     },
     "cts__timing__hold__ws": {
-        "value": -21.0,
+        "value": -18.0,
         "compare": ">="
     },
     "cts__timing__hold__tns": {
-        "value": -84.0,
+        "value": -72.0,
         "compare": ">="
     },
     "globalroute__antenna_diodes_count": {
@@ -52,19 +62,19 @@
         "compare": ">="
     },
     "globalroute__timing__setup__tns": {
-        "value": -84.0,
+        "value": -368.0,
         "compare": ">="
     },
     "globalroute__timing__hold__ws": {
-        "value": -21.0,
+        "value": -18.0,
         "compare": ">="
     },
     "globalroute__timing__hold__tns": {
-        "value": -84.0,
+        "value": -72.0,
         "compare": ">="
     },
     "detailedroute__route__wirelength": {
-        "value": 126525,
+        "value": 125219,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
@@ -84,15 +94,15 @@
         "compare": ">="
     },
     "finish__timing__setup__tns": {
-        "value": -84.0,
+        "value": -171.0,
         "compare": ">="
     },
     "finish__timing__hold__ws": {
-        "value": -21.0,
+        "value": -18.0,
         "compare": ">="
     },
     "finish__timing__hold__tns": {
-        "value": -84.0,
+        "value": -72.0,
         "compare": ">="
     },
     "finish__design__instance__area": {
diff --git a/flow/designs/gf12/gcd/config.mk b/flow/designs/gf12/gcd/config.mk
index 92b24e8987..a1113f19f6 100644
--- a/flow/designs/gf12/gcd/config.mk
+++ b/flow/designs/gf12/gcd/config.mk
@@ -5,9 +5,11 @@ export PLATFORM    = gf12
 export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v
 export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
 
-# These values must be multiples of placement site
-export DIE_AREA    = 0 0 99.96 100.128
-export CORE_AREA   = 9.996 10.08 89.964 90.048
+export CORE_UTILIZATION  = 20
+export CORE_ASPECT_RATIO = 1
+export CORE_MARGIN       = 2
+
+export PLACE_DENSITY_LB_ADDON = 0.20
 
 export GLOBAL_PLACEMENT_ARGS = -skip_initial_place
 
diff --git a/flow/designs/gf12/gcd/constraint.sdc b/flow/designs/gf12/gcd/constraint.sdc
index 70b68ac65c..730311595a 100644
--- a/flow/designs/gf12/gcd/constraint.sdc
+++ b/flow/designs/gf12/gcd/constraint.sdc
@@ -2,7 +2,7 @@ current_design gcd
 
 set clk_name core_clock
 set clk_port_name clk
-set clk_period 280
+set clk_period 240
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/gf12/gcd/rules-base.json b/flow/designs/gf12/gcd/rules-base.json
index be993a7ad4..e25c47a515 100644
--- a/flow/designs/gf12/gcd/rules-base.json
+++ b/flow/designs/gf12/gcd/rules-base.json
@@ -1,11 +1,11 @@
 {
     "synth__canonical_netlist__hash": {
-        "value": "a5874bf0d7a4676c0e25a99a5c7f6fcc237ed682",
+        "value": "d8877e14f6cc83df1d67733f6bf3d9e8a9dac8bd",
         "compare": "==",
         "level": "warning"
     },
     "synth__netlist__hash": {
-        "value": "4289d9760a66cd6331d0d0a75d97005969ecace5",
+        "value": "308043d4a1cccf693410f3548be8b367ee18ffa4",
         "compare": "==",
         "level": "warning"
     },
@@ -18,11 +18,11 @@
         "compare": "=="
     },
     "placeopt__design__instance__area": {
-        "value": 472,
+        "value": 228,
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 974,
+        "value": 607,
         "compare": "<="
     },
     "detailedplace__design__violations": {
@@ -30,15 +30,15 @@
         "compare": "=="
     },
     "cts__design__instance__count__setup_buffer": {
-        "value": 85,
+        "value": 53,
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
-        "value": 85,
+        "value": 53,
         "compare": "<="
     },
     "cts__timing__setup__ws": {
-        "value": -21.5,
+        "value": -21.3,
         "compare": ">="
     },
     "cts__timing__setup__tns": {
@@ -46,7 +46,7 @@
         "compare": ">="
     },
     "cts__timing__hold__ws": {
-        "value": -14.0,
+        "value": -12.0,
         "compare": ">="
     },
     "cts__timing__hold__tns": {
@@ -58,15 +58,15 @@
         "compare": "<="
     },
     "globalroute__timing__setup__ws": {
-        "value": -26.3,
+        "value": -26.0,
         "compare": ">="
     },
     "globalroute__timing__setup__tns": {
-        "value": -250.0,
+        "value": -435.0,
         "compare": ">="
     },
     "globalroute__timing__hold__ws": {
-        "value": -14.0,
+        "value": -12.0,
         "compare": ">="
     },
     "globalroute__timing__hold__tns": {
@@ -74,7 +74,7 @@
         "compare": ">="
     },
     "detailedroute__route__wirelength": {
-        "value": 4449,
+        "value": 2026,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
@@ -94,11 +94,11 @@
         "compare": ">="
     },
     "finish__timing__setup__tns": {
-        "value": -56.0,
+        "value": -113.0,
         "compare": ">="
     },
     "finish__timing__hold__ws": {
-        "value": -14.0,
+        "value": -12.0,
         "compare": ">="
     },
     "finish__timing__hold__tns": {
@@ -106,7 +106,7 @@
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 490,
+        "value": 240,
         "compare": "<="
     }
 }
\ No newline at end of file
diff --git a/flow/designs/sky130hs/ibex/config.mk b/flow/designs/sky130hs/ibex/config.mk
index fcbea270cb..b94fd5e375 100644
--- a/flow/designs/sky130hs/ibex/config.mk
+++ b/flow/designs/sky130hs/ibex/config.mk
@@ -12,8 +12,8 @@ export SYNTH_HDL_FRONTEND = slang
 
 export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 
-export CORE_UTILIZATION = 45
-export PLACE_DENSITY_LB_ADDON = 0.2
+export CORE_UTILIZATION = 60
+export PLACE_DENSITY_LB_ADDON = 0.20
 export TNS_END_PERCENT = 100
 
 export REMOVE_ABC_BUFFERS = 1
diff --git a/flow/designs/sky130hs/ibex/constraint.sdc b/flow/designs/sky130hs/ibex/constraint.sdc
index 500c60abcf..1215493a44 100644
--- a/flow/designs/sky130hs/ibex/constraint.sdc
+++ b/flow/designs/sky130hs/ibex/constraint.sdc
@@ -2,7 +2,7 @@ current_design ibex_core
 
 set clk_name core_clock
 set clk_port_name clk_i
-set clk_period 7.0
+set clk_period 6.5
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/sky130hs/ibex/rules-base.json b/flow/designs/sky130hs/ibex/rules-base.json
index 438bf92fe1..2fc6ca0068 100644
--- a/flow/designs/sky130hs/ibex/rules-base.json
+++ b/flow/designs/sky130hs/ibex/rules-base.json
@@ -42,15 +42,15 @@
         "compare": ">="
     },
     "cts__timing__setup__tns": {
-        "value": -3.2,
+        "value": -57.7,
         "compare": ">="
     },
     "cts__timing__hold__ws": {
-        "value": -0.35,
+        "value": -0.325,
         "compare": ">="
     },
     "cts__timing__hold__tns": {
-        "value": -1.4,
+        "value": -1.3,
         "compare": ">="
     },
     "globalroute__antenna_diodes_count": {
@@ -62,19 +62,19 @@
         "compare": ">="
     },
     "globalroute__timing__setup__tns": {
-        "value": -338.0,
+        "value": -604.0,
         "compare": ">="
     },
     "globalroute__timing__hold__ws": {
-        "value": -0.35,
+        "value": -0.325,
         "compare": ">="
     },
     "globalroute__timing__hold__tns": {
-        "value": -1.4,
+        "value": -1.3,
         "compare": ">="
     },
     "detailedroute__route__wirelength": {
-        "value": 824415,
+        "value": 783228,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
@@ -90,19 +90,19 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -0.35,
+        "value": -0.861,
         "compare": ">="
     },
     "finish__timing__setup__tns": {
-        "value": -62.1,
+        "value": -291.0,
         "compare": ">="
     },
     "finish__timing__hold__ws": {
-        "value": -0.35,
+        "value": -0.325,
         "compare": ">="
     },
     "finish__timing__hold__tns": {
-        "value": -1.4,
+        "value": -1.3,
         "compare": ">="
     },
     "finish__design__instance__area": {