Merge pull request #4535 from The-OpenROAD-Project-staging/tighten-aes_lvt-spi

update ihp-sg13g2/spi and asap7/aes_lvt configs

Author: vvbandeira

flow/designs/asap7/aes_lvt/constraint.sdc

@@ -1,6 +1,6 @@
 set clk_name clk
 set clk_port_name clk
-set clk_period 360
+set clk_period 310
 
 # Match the old set_input/output_delay = 0.2 * clk_period budget, as
 # optimization targets only (no set_input/output_delay — see rationale in

flow/designs/ihp-sg13g2/spi/config.mk

@@ -6,8 +6,8 @@ export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.
 
 export USE_FILL = 1
 
-export PLACE_DENSITY ?= 0.88
-export CORE_UTILIZATION = 20
+export PLACE_DENSITY = 0.9
+export CORE_UTILIZATION = 60
 export TNS_END_PERCENT = 100
 
 export SWAP_ARITH_OPERATORS = 1

flow/designs/ihp-sg13g2/spi/constraint.sdc

@@ -2,7 +2,7 @@ current_design spi
 
 set clk_name core_clock
 set clk_port_name clk
-set clk_period 1.0
+set clk_period 0.8
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]