memory_image_pkg.vhd

library ieee;
use ieee.std_logic_1164.all;

library work;
use work.mem_pkg.all;

-- memory_image_pkg -- GENERATED FILE. Do not edit by hand.
--
--   source:   sw/slots4.s
--   assembler: tools/pasm.py
--
-- Regenerate with:
--   python tools/pasm.py sw/slots4.s -o memory_image_pkg.vhd
--
-- On an FPGA, block RAM is initialised from the configuration bitstream, so
-- "RAM with initial contents" is not a contradiction: the image arrives when
-- the chip is configured and can be overwritten afterwards through the data
-- bus. The split between banks is a CONVENTION, not a constraint -- both are
-- ordinary read/write memory in one address space.
--
--   bank 0 -> addresses   0..255
--   bank 1 -> addresses 256..511

package memory_image_pkg is

    constant BANK0_INIT : word_array(0 to 165) := (
        0   => X"0C1D01EF",
        1   => X"0C180140",
        2   => X"0C10000A",
        3   => X"38000058",
        4   => X"38000071",
        5   => X"0C080001",
        6   => X"0608480B",
        7   => X"29200018",
        8   => X"06088001",
        9   => X"3800001A",
        10  => X"38000029",
        11  => X"38000035",
        12  => X"1CD10000",
        13  => X"38000087",
        14  => X"38000087",
        15  => X"22200012",
        16  => X"3800005B",
        17  => X"38000087",
        18  => X"06118000",
        19  => X"0C0803E8",
        20  => X"0608480B",
        21  => X"29200017",
        22  => X"0C1003E7",
        23  => X"34000003",
        24  => X"0C10000A",
        25  => X"34000003",
        26  => X"17BD0001",
        27  => X"1BBF0000",
        28  => X"0C0D0000",
        29  => X"0C080004",
        30  => X"21A80026",
        31  => X"080401F4",
        32  => X"0C05000A",
        33  => X"38000090",
        34  => X"070D4800",
        35  => X"19270000",
        36  => X"11AD0001",
        37  => X"3400001D",
        38  => X"0BBF0000",
        39  => X"13BD0001",
        40  => X"3FE00000",
        41  => X"0B080000",
        42  => X"05004308",
        43  => X"0B090001",
        44  => X"05204A08",
        45  => X"05094005",
        46  => X"0B090002",
        47  => X"05204908",
        48  => X"05094005",
        49  => X"0B090003",
        50  => X"05094005",
        51  => X"180801F5",
        52  => X"3FE00000",
        53  => X"0C060000",
        54  => X"0C0D0000",
        55  => X"0C080004",
        56  => X"21A80046",
        57  => X"070D4800",
        58  => X"092A0000",
        59  => X"0C0E0000",
        60  => X"0C080004",
        61  => X"21C80044",
        62  => X"070E4800",
        63  => X"092B0000",
        64  => X"294B0042",
        65  => X"10C60001",
        66  => X"11CE0001",
        67  => X"3400003C",
        68  => X"11AD0001",
        69  => X"34000037",
        70  => X"0C080010",
        71  => X"28C8004A",
        72  => X"0C060032",
        73  => X"3FE00000",
        74  => X"0C08000A",
        75  => X"28C8004E",
        76  => X"0C060008",
        77  => X"3FE00000",
        78  => X"0C080008",
        79  => X"28C80052",
        80  => X"0C060004",
        81  => X"3FE00000",
        82  => X"0C080006",
        83  => X"28C80056",
        84  => X"0C060001",
        85  => X"3FE00000",
        86  => X"0C060000",
        87  => X"3FE00000",
        88  => X"0C0F000C",
        89  => X"1E040000",
        90  => X"3400005E",
        91  => X"0C0F000A",
        92  => X"1E240000",
        93  => X"3400005E",
        94  => X"17BD0001",
        95  => X"1BBF0000",
        96  => X"0C05000A",
        97  => X"38000090",
        98  => X"1CED0000",
        99  => X"0C05000A",
        100 => X"1CC40000",
        101 => X"38000090",
        102 => X"1CEE0000",
        103 => X"05E04308",
        104 => X"04C04A08",
        105 => X"05094005",
        106 => X"05C04908",
        107 => X"05094005",
        108 => X"050D4005",
        109 => X"180801F5",
        110 => X"0BBF0000",
        111 => X"13BD0001",
        112 => X"3FE00000",
        113 => X"17BD0001",
        114 => X"1BBF0000",
        115 => X"0C0F0002",
        116 => X"080801F3",
        117 => X"050F4004",
        118 => X"21000074",
        119 => X"38000082",
        120 => X"080801F3",
        121 => X"050F4004",
        122 => X"21000074",
        123 => X"080801F3",
        124 => X"050F4004",
        125 => X"2900007B",
        126 => X"38000082",
        127 => X"0BBF0000",
        128 => X"13BD0001",
        129 => X"3FE00000",
        130 => X"0C0802BC",
        131 => X"21000086",
        132 => X"15080001",
        133 => X"34000083",
        134 => X"3FE00000",
        135 => X"0C080096",
        136 => X"2100008F",
        137 => X"0C090064",
        138 => X"2120008D",
        139 => X"15290001",
        140 => X"3400008A",
        141 => X"15080001",
        142 => X"34000088",
        143 => X"3FE00000",
        144 => X"0C060000",
        145 => X"0C070000",
        146 => X"20A000A3",
        147 => X"0C080020",
        148 => X"1C890000",
        149 => X"0C0C0001",
        150 => X"210000A2",
        151 => X"04E03848",
        152 => X"052057C9",
        153 => X"04EA3800",
        154 => X"05204848",
        155 => X"04C03048",
        156 => X"04E5580B",
        157 => X"296000A0",
        158 => X"04E53801",
        159 => X"04CC3000",
        160 => X"15080001",
        161 => X"34000096",
        162 => X"3FE00000",
        163 => X"0C06FFFF",
        164 => X"1C870000",
        165 => X"3FE00000"
    );

    constant BANK1_INIT : word_array(0 to 0) := (
        0   => X"00000000"
    );

end package memory_image_pkg;

-- Made with my soul - Swately <3