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Hi , I’m working on a MAX7219 LED matrix project using a MAX II CPLD and VHDL. Right now:
Symptoms:
What I already checked:
I suspect it may be:
Has anyone experienced something similar with MAX7219 + FPGA/CPLD? Any advice would help a lot 😅 Thanks! |
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Answered by
LgMets10
May 22, 2026
Replies: 1 comment 1 reply
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Try my MAX7219x4 component (at Interface.vhd) first. Make the necessary edits for your 3 arrays, make sure MainCLK doesn't exceed the spec, set Matrix 1-3 to test values. Does it work? |
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Thanks for the help
I finally got the 4 MAX7219 matrices working correctly with my CPLD project.
The problem ended up being mostly timing and initialization related.
I slowed down the SPI clock a lot, added startup delays, repeated the initialization sequence, added display-test commands, and also extra latch delays. After that everything started working perfectly.
Your MAX7219x4 example helped me understand the timing much better honestly.
Now I can finally continue with the Arkanoid project