RyuSim does not expose SV interface instances through VPI

[stonelyd]

Summary

RyuSim does not expose SystemVerilog interface instances as child objects through the VPI layer, causing cocotb tests that access interface ports to fail.

Reproduction

Using taxi-on-ryusim (https://github.com/Seiraiyu/taxi-on-ryusim), run the taxi_axis_fifo test:

cd src/axis/tb/taxi_axis_fifo
make SIM=ryusim

Expected

cocotb can access dut.s_axis and dut.m_axis (SV interface instances on the top-level module).

Actual

AttributeError: test_taxi_axis_fifo contains no child object named s_axis

All 14 sub-tests fail with the same error at TB.__init__ when trying to construct AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), ...).

Context

The SV testbench wrapper (test_taxi_axis_fifo.sv) instantiates taxi_axis_if interfaces and connects them to the DUT. RyuSim compiles and elaborates this correctly (verified with 1.6.0 + -G params), but the VPI handle iteration does not return the interface instances as children of the top-level module.

This blocks all 162 taxi tests — every test accesses at least one interface instance on the DUT.

Environment

• RyuSim 1.6.0
• cocotb 2.1.0.dev0 (Seiraiyu fork)
• cocotb-bus 0.3.0