v10 Discussion / Ideas

[Rootthecause]

DCDCv10 Development

Dear interested readers,
this is the announcement for the development of the 10th DCDC version.
As in the spirit of open source, I will keep the design and development process transparent, starting with this post.
I highly value ideas, feature requests and feedback from you and like to encourage to participate in the design and development.

You can help improving the upcoming version by filling out my survey. Thanks a lot!

Aside from some basic considerations, there is nothing done yet (there is a v10_dev branch now, but currently containing the v9-3). This post is merely to start the thinking process an gather ideas for version 10.

Design approach
The old approach was to make the converter very efficient and the PCB as compact as possible.
Although this worked somehow, there are certainly better ways to design something for global replication.
So the new design approach will be focusing on making it easy to manufacture and compact as a whole - not just the PCB.
This goal could be achieved by making the PCB larger and implementing a planar transformer (less total height).
The larger PCB will also help to passively dissipate heat, running cooler (less thermal stress, longevity) and requiring less active cooling (maybe full passive operation possible?) which would further increase efficiency.

Design Goals

• easy to manufacture
• reliable
• efficient: 90% at 50W load, peak 97.5% or more (allowing passive cooling)
• larger PCB but lower height profile (less volume)

Outlines for v10 and features (subject to change)

• Topology: LLC Halfbridge (unchanged)
• GaN HEMTs for half bridge and active rectification (previously SiC + Si)
• Planar Transformer (either integrated into the main PCB or as solderable daughter board, 24V will be the main version, a 12V version is likely), isolation by design (no isolation testing required)
• Switching frequency 250 kHz to 750 kHz (roughly)
• Controller: STM32 (allows custom functions, direct halfbridge/loop control), located on LV side
• CAN interface (using STM32)
• Isolated gate drivers
• standby features: auto shutdown, light load mode, output load sensing if e.g. the LVMS is enabled or not
• same internal power supply but with improved capacitor and UVLO
• no internal 12V supply, 5V and 3.3V only (if possible)
• All components shall be rated for a working temperature of at least 105°C

Optional Features

• Full Input/Output voltage and current monitoring (live efficiency optimization, dynamic dead time control)
• CV/CC output Mode
• Load sharing (if multiple DCDCs are paralleled)
• fault logging to flash
• precharge-less (or simplified precharge)
• 3D-Printable housing/cover for touch protection and/or airflow conduit
• switching frequency variation for lower EMI emissions

Removed Ideas/Features

• removed passive HV LED (draws ~500 mW at 600V - thats just too much to hit the efficiency goal, but might remain optionally)

Timeline (roughly)

• Gathering ideas until end of November 2025
• PCB Design until end of January 2026
• Ordering and (Beta-)testing in February/March 2026
• Release DCDCv10 in April 2026

Note: I’m currently writing my bachelor thesis - so I won’t be very active probably till the end of October 2025.
The proposed timeline might be complete rubbish depending how my life goes after my bachelors degree.
If your team is interested in building the DCDC, I suggest building the DCDCv9-3r until the v10 is fully tested.

Support/Help
If you like to speed up the development of v10 by providing your help, I would be very grateful.
Especially the STM32 programming part is something I like to hand over to someone experienced (or you'll have to deal with my spaghetti code).

In the following areas any support would be appreciated

• Software development (STM32) and Microcontroller selection (current favorite: STM32G474CET6, supports HRTIM), Pin Mapping
• Planar Transformer development
• Sourcing Testing equipment HV-Source + LV-Sink for faster and more accurate efficiency tests

[Rootthecause]

Hello Everyone!
I’m sorry for the delayed update - my thesis was rough on me, but it was worth it. I hope, I can now fully focus on the project.

In the last months a few teams contacted me regarding the v9-3 for FS Events 2026.
I want to clarify, that the v9-3 in it's current state might be not fully rules conform see #10.
To avoid discussions with Scurtis, teams should find solutions to this. I'm open to implement proposed solutions by teams into the documentation, but my current focus is on the v10, so I cannot actively develop solutions for the v9-3.
I wish I could recommend building the v10 instead, but I do not expect ordering the first prototype before end of February or March.
As the v10 is the first version which requires software, I expect additional development time in addition to the hardware, which I currently cannot quantify - but I'm aware of 3 people who offered their help via the v10 survey 🫶🏻 so I hope this works out well.

---

Thanks to all who participated in the survey! Here are the results with some thoughts added :)

tl;dr:

The v10 currently is planned to have the following specs based on your answers:
Input Voltage range: 250 to 600 V
Output Voltage: 24 V

peak Power: 1000 W
max. continuous Power: 800 W

Additional Features which may or may not be implemented depending on required time:

• Parallel operation (load sharing)
• second Output Voltage: 1 to 24 V output with constant current regulation (via Step-Down)

Regarding everyone who showed interest in helping out via the survey form: I will try to get in touch with you during the next days. Please join the for faster communication and meetings.

---

Long form

Here are the Results from the survey.

In total 31 teams/people have participated. I had to remove three entries because they where either out of scope for formula student or had been filled in incorrectly.

The goal of this survey was to find a design which fits all needs. However, some requirements are hard to fulfil, e.g. a 60 V output version. So the final design shall fit most needs.

Input Voltage

From the chart it can be seen, that most teams are using 600 V as upper limit. The lower limit is 250 V.
This is good, as the current DCDCv9-3r managed an input range of 200 V to 600 V (however due to an regulation issue it is currently either 200 V to 550 V or 250V to 600V depending on setting).
So in other words, it should doable to achieve this input range. Due to the STM32 being newly utilised in the v10, new control strategies can be used to further increase the voltage range.
However, having a large input range can decrease overall efficiency if the output power shall remain the same for lowest input voltage.
For example: if you need 500 W at an input range of 400 V to 600 V you can hit 97% efficiency. But if you still need 500 W at 200 V then the resonant circuit needs to be oversized, allowing for e.g. 1000 W at 400 V.
Even if you don’t require this power at 400 V, there would much higher currents cycling in the resonant circuit decreasing the efficiency to probably < 95%.

In this case, the most efficient option would be to create two DCDC versions, like 350 V to 600 V and 250 V to 450 V. However this would require two different designs - this is against the design approach.
There are only 3 Teams requiring 350 W, 400W and 600 W (average) at 250 V. While 400 W can be likely meet at 250 V, the 600 W are out of scope. In this case I would advise the team to operate 2 DCDCs separately (parallel operation might be possible, but has currently no priority in development).

If you’re familiar with lithium batteries, you know that most commonly used chemistries in FS having a voltage range of 2.5 V to 4.2 V (some are up to 4.35 V but not that common).
So if 144 cells in series are used to reach 604,8 V, the lower voltage is 360 V. So why there are teams requiring lower than that?
One team messaged me, that they want to use the DCDC for two different batteries, one was up to 600 V and the other up to 450 V - valid point.
Another reason I could think of are high discharge currents, dropping the voltage to 2 V for a few seconds (which is allowable for some cells), resulting in 288 V min.
You also don’t want to have your LV-System shut down before the motor controller does under high load.

For the upper limit all agree on 600 V as this is the current max. voltage allowed according to the rules. For reliability and safety reasons the actual max. working voltage will be 620 V.
There was a comment in the survey about 800 V being rumoured as new upper max. voltage for next year. In the rules feedback I was indeed able to spot the 800 V proposal.
Although I go with the idea in general, as the automotive industry is adopting to 800 V systems, the benefits in FS are rather small, and the changes required rather large.
Also the FSG data logger would need to support this. As the Rules 2026 v1.1 have been released, the max. voltage is still at 600 V.
But I could imagine that there will be a change at some point to 800 V, so I may implement higher spacings wherever possible, just for good engineering practice / clearances and easy change later.

Result: Input voltage Range from 250 V to 600 V
(This result is open for further discussion - please comment below if you want to discuss this.)

Power Requirement

Three answers with „don’t know yet“ are defaulted to manual driven cars.

I originally expected to see a large difference between driverless and manual driven cars. But the survey revealed that both categories are similar in range.
Some data points are interesting, like the 50 W average consumption for a driverless team.
I changed the maximum power definition from being able to deliver it for 60 Seconds in the v9-3r to 10 Seconds for the v10.
The reason for this change lies in the practical application for driverless teams: There is only a limited amount of steering possible. If you steer faster (more power) you will reach the required angle in shorter time.
So the peak power is probably only required for a few seconds. On the other hand it makes it easier to achieve the thermal properties and find suiting fuse ratings.
If someone would be willing to share their autonomous power draw, this would help a lot! Also one comment was about bi-directional conversion for autonomous systems. I really wonder how bad the reverse current is. Currently I do not plan to implement bi-directional conversion for the first v10-1 version, because this adds another layer of issues.

After some data grouping I found three fields for average power:

• up to 400 W (12 entries)
• up to 800 W (12 entries)
• up to 1500 W (3 entries)

This grouping would be the best approach for highest efficiency. However, this does not meet the minimalist goal of the design.
So here’s the idea:
The 400 W group is merged into to 800 W group. The efficiency decrease is not an issue.
The 1500 W group uses 2x 800 W converters.
This leaves us with one design focused on 800 W max. average.

The max. peak Power can be grouped similarly:

• up to 500 W (11 entries)
• up to 1000 W (10 entries)
• up to 2000 W (6 entries)

Doing the same as before leaves us with 1000 W max. peak.

Result: Power Requirement: 800 W Average, 1000W peak (10s).
Teams requiring more are advised to use two DCDCs.
(This result is open for further discussion - please comment below if you want to discuss this.)

Output Voltage

The vast majority of teams is using 24 V. The other large group is using 12 V. Only 10.8 % is using something else.
The minimalist design approach would ask for a 24 V only version. But you cannot merge the 12 V and 24 V together like for the power requirements - or can you? [Vsauce music starts playing]
A preliminary planar transformer design showed, that it would be difficult to design the required winding ratio of 32:1 needed for a 12 V version. There is a way of getting a 16:0.5 ratio, but this would need a very different design.
So the 12 V version seems hard to achieve in general.
There was also a comment asking for 24 V and 48 V dual output… hm.
There are ways to do voltage doubling as well as halving (aka current doubling), but they require highside switching and make things rather complicated, especially as you can only control one output voltage from the primary side (the other output is then only somewhat regulated). We would need something like a second voltage controller…
What about using a second DC/DC after the LLC DCDC?

So here’s the plan: The main output will be 24 V. But there is a optional step-down DC/DC using the LM5190-Q1 to deliver 12 V.
Additionally the step down features constant current control to limit inrush currents of large LV capacitors or as a overcurrent protection in general.
Also teams not requiring 12 V can use it as a adjustable supply anywhere between 1 V and 24 V, so the 24V output can feature constant current control as well.
This might sounds nice over all, but requires additional designing and testing. In doubt, this will be not integrated into the main DCDC pcb but will implemented as an expansion board instead.
In future versions, the step down could be controlled by the STM32 as well, also monitoring the output voltage and current - but at the moment this seems too risky to implement in the given amount of time.

Result Output Voltage: 24 V with the possibility of 12 V (adjustable) via Step-Down.
Teams requiring more than 24 V can implement a Step-up converter on their own.
A native 48 V seems also possible by using a 16:2 transformer ratio, allowing for 48V/24V dual output, but it might be tricky with the leakage inductance having some imbalance.
(This result is open for further discussion - please comment below if you want to discuss this.)

Weights of design choices
The survey featured a scale from 1 (not important) to 5 (very important) for design aspects compared to the cost.
Example: „The DCDC should be rather be Inexpensive (1) or Energy Efficient (5)“.
A score of 5 represents that energy efficiency is much more important than the costs of the converter, thus better but more expensive components/designs will be chosen.
Note: As the scale goes from 1 to 5 the neutral point is 3 and not 2.5.

The DCDC should be rather be...

Inexpensive (1) or Reliable (5) - Average Score: 4.3
Inexpensive (1) or Energy efficient (5) - Average Score: 3.5
Inexpensive (1) or Easy to build (5) - Average Score: 3.0
Energy efficient (1) or Small in size (5) - Average Score: 3.3

Reliability scores high with 4.3 - not a surprise - if the LV supply fails, then everything else won’t work as well.
This has a direct influence on my design: I was planning to use GaN HEMTs for the half bridge, however I decided to keep using SiC MOSFETs as their safe operating area it less strict.
Also the currently available SiC FET have higher voltage models available, so 900 V or even 1200 V versions might be used.
However, using SiC instead of GaN will lead to higher losses. I’ve done some simulations where GaN (GS66516B-TR) would result in 0.33 W losses at full load (1130 W out) per half-brige FET at 600 V / 550 kHz. A somewhat similar SiC Device (IMBG65R020M2HXTMA1) would result in 0.75 W. Although the GaN has 2.3 times less losses, both seem very low in my opinion - so low that I start questioning the simulation.
The only way to truly verify those simulations is testing it in real life.

For the active rectification I want to use SiC as well, but GaN might have even lower losses here. Currently I’ve got no simulation to figure out the losses. Paralleling FETs might be an option here too.

Inexpensive (1) or Energy efficient (5) - Average Score: 3.5
I see. Efficiency is for many not that important compared to costs, but actually it can make the design simpler as the thermal management is less complicated.

Inexpensive (1) or Easy to build (5) - Average Score: 3.0
For what I can currently say, the v10 will be easier to manufacture and test than the v9-3. There might be not really a way to save costs by increasing the build effort.

Energy efficient (1) or Small in size (5) - Average Score: 3.3
This one is supports my new design. Although making the PCB credit-card-sized is somewhat cool, as everyone roughly knows this size, it makes the design much harder.
The v10 will be use a larger PCB but less in height, maybe 20-30 mm.

Costs
The survey made clear, that 75% of the teams would be willing to spend 300€ or more for a DC/DC converter which would fulfil their specs.
The old v9-3 was around 150€ in components. I expect the new design in the range of 200 to 300€ as the transformer consists of two custom spec’ed PCBs and some components are chosen for higher safety margin.

Miscellaneous

• I’ve build a LLC simulation model which does not require any additional models to be downloaded, except if you want to simulate somewhat accurate losses on the half-bridge FETs. The benefit of it is a huge increase in simulation speed of around 100 µs simulation in 10 seconds. However the downside is the currently fixed switching frequency, but this is fine for loss estimation. I'll release this on the v10 branch soon.
• I was able to test the PCB transformer based on the „pcb-transformer-test“ files in the v9-3 design. The losses where rather low, despite being only 1 OZ 2-Layer pcbs, equal to 0.105 mm^2. The proposed design might use 4 Layer PCBs with 1.26 mm^2 copper (12x more), but it is hard to estimate in advance how skin- and proximity effects will influence the losses.
• I made a preliminary transformer design based on Ferroxcube E43/10/28-3F36 cores. Their core material seems the best in terms of losses compared to TDKs materials. The design will have 50 mT max flux density at 500 kHz. This would lead to 2.1 W of core losses in an ideal setting (this would be very low compared to the approx 5-10W of losses in the v9-3).

[Rootthecause]

Happy new Year everyone! 🥳

This is a general update on the current development of the DCDCv10.
It’s not only me anymore - we’re three active developers now (2x software, 1x hardware (me)) with regular meetings every week.
This should help getting the converter operational faster when the hardware is done.
However, currently it's still too early to say when this will be. The schematic is still in a early stage with many changes pending.
I hope at least to finish the PCBs for the transformer soon for a order and new measurements.

What's new?

Planning

• Google Sheet for Developers (only) for co-working
• Tool to keep track of functions for implementation together with priority assigment and status of implementation
• New Repro for DCDCv10 Software (currently private)

Software & STM32

• The STM32 was changed from the STM32G474CET6 (48 Pin) to the STM32G474RET3 (64 Pin version) in order to support programmable current and voltage of the second output rail as well as U/I measurement of it
• basic STM32 pin assigment was completed
• STM32 Nucleo boards have been ordered for early software testing on hardware

Hardware

• GaN HEMTs were considered too unsafe due to their very limited SOA and impractical packaging (cooling / chip breaking / replacement). Their half bridge power losses where in some cases 50% of SiC, but the best SiC was below 2 W losses at 1000W load, which is still very efficient.
• Simulations where completed for selecting the best half bridge SiC FET
• The gate voltage was raised from 12 V to 15 V for lower losses on the half bridge and synchronous rectification
• New output connector: Molex Mini-Fit supporting up to 50 A and positive locking
• Transformer mock-up with 3D-Printed windings, first measurements showed good alignment of the measured inductance values with the calculation. Those measurements where used to refine the LTspice model and revealed a mistake in previous simulations which was causing large amounts of ringing on the secondaries.
• refined secondary winding PCB design based on new measurements and simulation

[Rootthecause]

Hi everyone!
It was quite some work implementing all the new stuff for the DCDCv10.
Today I like to present the first version of the v10 schematic.

DCDCv10-0_260128.pdf

If you spot an error, please let me know in a comment below :) 
I will try to update the kicad files in the v10_dev branch in the next days, when I'm done with assigning footprints and sorting files.

Although I've figured out almost all components, there might be some changes during the next phase: Designing the PCB.
My goal is to fit everything on a 100 x 70 mm PCB (same as Version 7 and 8) with a total height of max. 25 mm.

Picture: left side: components, right top: 100x70 mm PCB, right bottom: PCB winding of the new transformer design.

However, as you can already see, the 4-Pin Molex Mini-Fit connector (the second component in the left top corner) is not mini at all. For comparison I put a XT60 connector left to it. You could probably fit 4x XT90 straight connectors in the same footprint. The straight variant of the Molex is not an option, as it would be too tall. I might switch to an angled version of the XT90 (for 24V output) and XT60 (for 12V output). Either way, it will probably get very, very hard to fit everything together in this tight space. **Please leave room for a 120 x 90 x 30 mm worst-case Design!**

As component selection is mostly done, I can also give a rough cost estimate.
Currently all components (excluding PCBs and maybe a small fan) are ~ 210€ from Mouser (excl. taxes).

The PCBs for the transformer are unfortuantely rather expensive due to the required specs.
PCBs with the following specs can be ordered at JLCPCB.
Primary: ~30€ (10 PCBs, 8 required), 4 Layer, Outer copper: 1 OZ, Inner copper 0.5 OZ, thickness: 0.6 mm (imporant!)
Secondary: ~40€ (5 PCBs, 3 required). 4 Layer, Outer copper: 1 OZ, Inner copper 2 OZ, thickness: 0.8 mm (can be thicker, but does not lower costs, might perform worse when thicker. It may be possible to reduce costs with lower copper weight if less power is required - must be tested!)
Main PCB: ~33€ (5 PCBs, 1 required). 4 Layer, Outer copper: 1 OZ, Inner copper 2 OZ, thickness: 1.2 mm (imporant!)
The costs can be reduced a lot if more than the minimum quantity is ordered.

The total costs with PCBs might be around 320 ± 20€ (excl. taxes).
I'm aware, that this is double the costs of the previous version, but please keep in mind, that this pretty much aligns with the set design goals. Also the costs can be reduced if the adjustable high power step down is not required (24V only) or less power is needed (cheaper MOSFETs).

Timeline Update

• Now: I am currently a week behind my own schedule in terms of completing the schematic.
• Next up: I need to do some adjustments on the PCB-Transformer design, as the mock-up revealed an issue when using only one zip-tie (note: The design will use glue and high temperature zip-ties for maximum reliability).
  I'll try to order the PCBs for the transformer before Chinese New Year.
• end of March: Finish the main PCB design + Software prototype.
• first prototype tests: mid April

On the software side there is currently no real progress due to the examen phase.
Good luck everyone with their exams! 🍀

v9-3 or v10 ?

I currently do not recommend anyone to drive the v10 in this season, except to those actively developing it.
There are currently just too many changes on the design, where something can be messed up - and I'm pretty sure that it will.
I might be able to resolve it, but that takes time. Even if it would take just 1 week to build and test the converter, I cannot guarantee that it will be before the events. The earliest update on validating the design is currently end of april.
Please also do not expect any documentation or build guide for the v10 in the coming months, as my current priority is hardware (and software for the software guys).

Regarding the rules issue about the voltage rating of the litz (500V instead of 600V):
I'm currently in touch with a team trying to resolve this by setting up an order at Elektrisola. Apperantly they offer HF litz with higher voltage rating. However, it's not a simple order, but rather a custom request. We currently don't know if they can offer low quantities and at which price. [← I'll keep this section updated, not updated since 29th of January 2026]

In my personal opinion, for a typical wire inside the TSAC, those rules (EV 5.4.7, EV 4.5.2, EV 4.5.3, EV 4.5.5) make total sense. You don't want two wires next to each other to not isolate enough.
However, the HF-litz on the transformer is next to no other wire where the max. TS voltage rating would make sense - and it also shouldn't due to the keep out area.
If the HF-litz is treated as wire, any PCB trace would be a "wire" as well and also require a 600V rating - which they don't.
If the conformal coating is argued as solution for PCBs, then why wouldn't it be sufficient for the transformer as well (which is already required)?
I whish to have more feedback on this matter from Scrutineers - maybe we try solving something which is not really relevant or can be seen as not relevant in this very usecase.

[Rootthecause]

Hi everyone!

Since the last update 2 months ago, much happened - but not as much as I'd like.
Currently about 60% of all connections in the PCB are routed, which currently looks like this:



Note: This is just a preview, some components are not properly placed yet.

The size of the v10 is currently 100 x 85 x 32 mm.

I've also got the PCBs for the planar transformer:

The black plastic between the cores/windings is just a place holder for the main DCDCv10 PCB, which is used as insulator between primary and secondary.

Problems

Half Bridge

Due to the restictions with insulation and signal layout, it is very hard to make a nice half bridge layout. I've redone this at least 5 times now and believe that there is no "nice" solution to this without other compromises, like having one of the FETs on the top of the PCB or putting the DC link cap further away. I've also tried finding a different DC link cap which is better suited for the layout with no luck.

PCB Transformer

The main idea of the PCB transformer design was to reduce proximity losses by using Dowell's curves. Using a single layer winding would be much better than having multiple layers (= multiple turns on one layer). This resulted in the stack-up of 7 pcbs with 0.6 mm thickness and 2 layers with one winding per layer (= 14 windings in total). There is also a variant with a 4 layer design with 2 parallel windings per PCB, but I was unable to order it during chinese new year, despite the PCB being manufactured after that. Also the secondary winding with 0.8 mm thickness is only 1 OZ instead of the planned 2 OZ.

At least this saves some money and still would give an idea of it's performance (and flaws...).

In the following picture, you can see the resistance of the coils (not impedance!) depending on frequency.
Every coil has a serial number. The PCB primary is Number 71.

The intended nominal switching frequency is 500 kHz and the max. primary current is 7.3 A_rms.
At this frequency, the primary resistance is 1.2 Ohm. So this would result in 64 W power dissipation over the transformer (core+primary). From other tests, I estimate that the maximum allowable continous power dissipation over the primary + core is around 10 W. So this is totally not possible with that PCB primary at 500 kHz. But why?

I've considered Dowell (=Proximity-Effect), Skin-Effect and core losses. But there is something I've totally missed: Eddy currents.
Although eddy currents are the root cause of Skin- and Proximity-Effect, it also causes to heat up large flat windings like a pan on a induction stove. This got very obvious when I tested the planar transformer: The secondary windings got very hot despite not having any load attached.
Splitting the winding into multiple parallel traces might reduce eddy currents, but probably leads to uneven current distribution, heating up the inner windings. To compensate for that, something like twisting the traces like in HF litz wire would be required - but is hard to accomplish on a PCB and has other drawbacks.

This has currently lead to a halt of the PCB approach. But I've tried other kinds of windings:

If you want to compare their resistance, the number on the windings is the same as in the measurement from before.

You can see, that winding 78 has the least resistance below 300 kHz. However, at higher frequencies all windings start to perform equally bad. Doing a test with a large single turn of different wires revealed, that the resistance is in most cases much higher than expected mathematically purely from skin-effect. This led to questioning the impedance measurement capabilities of the Analog Discovery 2 with it's Impedance Analyzer Extension Board.
I'm currently investigating this matter by seeking a professional impedance analyzer but also by building the Redako-PDNAnalyzer extention board.

v9-3 or v10 ?

With the ongoing transformer issues, the PCB design has come to a halt, as without a properly working transformer, the whole concept would not work or requires a time expensive redesign. So this needs to be solved first.
With the release of the DCDCv9-3r1.4 update, the issues from #10 have been adressed, so that the v9-3 should be good to go for the 2026 events. So do not expect the v10 this season and build the v9-3 instead.

v9-4 ?

Lately I've been thinking of adressing some shortcomings in the power dissipation of the v9-3 but also that the overall design of the currently envisioned v10 is overblown for the actual task of "just" converting voltage - despite the fact that many features are merely a by-product of making the converter more safe.
Perhaps an updated version of v9-3 would be something to consider.

While doing experiments and calculations I enjoy tinkering around with alternate solutions. One of them I'd like to share, although it can't be directly used in the v9-3 or the v10 design:

By replacing the primary winding with winding 78 (HF litz 315 x 0.071 mm) with 7 windings on both sides (14 in total) and a single turn of 600 x 0.071 mm for the secondaries and utilizing the same planar core E43/10/28 from the v10, I was able to operate the transformer on the v9-3 with an input voltage of 50V and a output voltage of 24V at 109 W load and 286 kHz.
This is remarkable in many ways:
A) The primary current during this was 6.1 A rms. Despite the high HF current, it only got 90°C hot.
B) The core on the isolated side only got 63°C warm from the magnetic flux, which is very acceptable.
C) The halfbridge also conducted those 6.1 A rms, and reached only 98°C during this.
D) The resonant gain at this operation was 14.4 - which is incredibly high considering the large load.

Or to put it in simpler terms: 2153 AV (not W because it's almost purely reactive current) were sloshing around in the resonant tank and everything held up fine without any cooling fan. Nevertheless the efficiency was only 85.9% (17.9 W losses), but it shows the potential for the half bridge and the transformer.

Timeline update

The v9-3r1.4 release took out some pressure on developing the v10 - which is really what I needed right now after working straight 4 Months almost every day on this project. So I will to take it down a notch from the v10 development. Also both software developers are busy in their teams.

DCDCv10 PCB: not before end of summer 2026*
Software prototype: not before end of summer 2026*
First prototype tests: maybe Autumn 2026*

*if a solution for the v10 transformer is found till then.

Asking for help

If you already have experience with planar transformers and would like to help out, please don’t hesitate to contact me. I appreciate any help!

On another note, I'm running out of my private funds for this project. There have been zero ko-fi donations and also 0.00 € earnings from Amazon URLs. I do not ask being paid for the more then 3000 hours of work which have gone into this project, but unfortunately the components and materials are not free. So I highly apprechiate any donations, which are 100% going into this project and not my own pockets.
I'm also thinking about selling PCBAs or even fully functional converters. However, I'm unsure what legal issues could come with this. Also world wide shipping is kind of annoying due to taxes and goods declaration.
As it's currently unclear how I'll earn a living after having finished my degree, I might end up making a living from this project.

[itsme200]

Hello,
how come you use such a high inductance for the resonant circuit? For 500khz you would usually use single digit uH or even less. Most likely, the distance between the layers is also too big, as many high frequency planar transformers use a single PCB with 10-16 layers.

I will also paste a link for a 400V LLC design with planar transformer from EPC, they utilise a interesting topology if you would be interested. https://epc-co.com/epc/products/evaluation-boards/epc91110 . They also have a reference design for a 800V one, but they havent released all the design files like for the 400V one.

Also, if you havent yet, check out Saturn PCB Design Toolkit, they have a planar inductor calculator, altough its only for single layer.

Best of luck

[Rootthecause]

[Some points have been answered via DMs already, but I'll answer here as well for the interested reader.]

Hi!
There are many reasons for those design choices. Let me break it down one by one:

Inductance

For 500khz you would usually use single digit uH or even less.

Very interesting point, but the required inductance depends also on the input voltage.
If you look into the PMP20637 RevA Test report by Texas Instruments, they did a 390V to 48V converter, with Lp = 28 nH.
Many planar designs which I came across were for relatively low input voltage and are then connected in series for e.g. a 400V converter, so the required inductance is much lower.
But I intend to operate at 600V on a single converter, requiring much higher Lp.

Layers

Most likely, the distance between the layers is also too big, as many high frequency planar transformers use a single PCB with 10-16 layers.

A > 4 Layer design is not intended for this open source project, as higher layer counts make the choice of PCB manufacturer more limited and are also not cost-efficient at all. But one of the main points of my current design is the high isolation aspect, with the final intent of not requiring an insulation test, as a PCB is used as an insulator. So the primary and secondary can't be on the same PCB.
(Note: I've been thinking about another design, without an additional insulator PCB for an interleaved design, but this would require a large design change, which I'm currently not actively working on, but I might do some tests going in this direction).

Saturn PCB Design Toolkit

I just gave it a try - nice option if you're doing single-layer coils only, as far as I can see. But I did not choose to have multiple windings on one layer, as this increases the proximity effect exponentially (in theory - it's more complicated than that).
Currently, I use the values from the core datasheet to calculate the AL value, which is good enough for a first draft.