From dc9323d5996a4a7686f1a114c73c668780492435 Mon Sep 17 00:00:00 2001 From: Matvei Pashkovskii Date: Thu, 26 Feb 2026 13:24:11 +0200 Subject: [PATCH 1/8] feat: Add AMD accelerator detection and tracking in libfabric topology --- src/utils/libfabric/libfabric_topology.cpp | 91 ++++++++++++++++++---- src/utils/libfabric/libfabric_topology.h | 16 +++- 2 files changed, 92 insertions(+), 15 deletions(-) diff --git a/src/utils/libfabric/libfabric_topology.cpp b/src/utils/libfabric/libfabric_topology.cpp index eab2f263..0620dff3 100644 --- a/src/utils/libfabric/libfabric_topology.cpp +++ b/src/utils/libfabric/libfabric_topology.cpp @@ -35,6 +35,7 @@ nixlLibfabricTopology::nixlLibfabricTopology() : num_aws_accel(0), num_nvidia_accel(0), + num_amd_accel(0), num_numa_nodes(0), num_devices(0), topology_discovered(false), @@ -86,8 +87,8 @@ nixlLibfabricTopology::discoverTopology() { NIXL_ERROR << "Failed to discover hwloc topology"; return status; } - // Build nVidia accelerator to EFA mapping based on PCIe topology - if (num_nvidia_accel > 0) { + // Build accelerator to EFA mapping based on PCIe topology + if (num_nvidia_accel > 0 || num_amd_accel > 0) { status = buildAccelToEfaMapping(); if (status != NIXL_SUCCESS) { NIXL_ERROR << "Failed to build accelerator to EFA mapping"; @@ -189,7 +190,9 @@ void nixlLibfabricTopology::printTopologyInfo() const { NIXL_TRACE << "=== Libfabric Topology Information ==="; NIXL_TRACE << "Topology discovered: " << (topology_discovered ? "Yes" : "No"); - NIXL_TRACE << "Number of AWS accelerators: " << num_aws_accel; + NIXL_TRACE << "Number of NVIDIA accelerators: " << num_nvidia_accel; + NIXL_TRACE << "Number of AMD accelerators: " << num_amd_accel; + NIXL_TRACE << "Number of AWS Neuron accelerators: " << num_aws_accel; NIXL_TRACE << "Number of NUMA nodes: " << num_numa_nodes; NIXL_TRACE << "Number of EFA devices: " << num_devices; NIXL_TRACE << "EFA devices: "; @@ -215,7 +218,9 @@ std::string nixlLibfabricTopology::getTopologyString() const { std::stringstream ss; ss << "Libfabric Topology: "; - ss << "AWS_Accelerators=" << num_aws_accel << ", "; + ss << "NVIDIA_GPUs=" << num_nvidia_accel << ", "; + ss << "AMD_GPUs=" << num_amd_accel << ", "; + ss << "Neuron_Accelerators=" << num_aws_accel << ", "; ss << "NUMA=" << num_numa_nodes << ", "; ss << "EFA=" << num_devices << ", "; ss << "Discovered=" << (topology_discovered ? "Yes" : "No"); @@ -328,29 +333,41 @@ nixl_status_t nixlLibfabricTopology::discoverAccelWithHwloc() { num_aws_accel = 0; num_nvidia_accel = 0; + num_amd_accel = 0; // Find all PCI devices and log detailed information - static const char *vendor_names[2] = {"NEURON", "NVIDIA"}; hwloc_obj_t pci_obj = nullptr; while ((pci_obj = hwloc_get_next_pcidev(hwloc_topology, pci_obj)) != nullptr) { const bool is_nvidia_accel = isNvidiaAccel(pci_obj); - if (is_nvidia_accel || isNeuronAccel(pci_obj)) { + const bool is_neuron_accel = isNeuronAccel(pci_obj); + const bool is_amd_accel = isAmdAccel(pci_obj); + + if (is_nvidia_accel || is_neuron_accel || is_amd_accel) { std::string pcie_addr = getPcieAddressFromHwlocObj(pci_obj); // Get device and vendor info uint16_t vendor_id = pci_obj->attr->pcidev.vendor_id; uint16_t device_id = pci_obj->attr->pcidev.device_id; uint16_t class_id = pci_obj->attr->pcidev.class_id; - NIXL_TRACE << "Found " << vendor_names[is_nvidia_accel] << " accelerator " - << num_aws_accel << ": " << pcie_addr << " (vendor=" << std::hex << vendor_id + const char *vendor_name = is_nvidia_accel ? "NVIDIA" : + is_amd_accel ? "AMD" : "NEURON"; + + NIXL_TRACE << "Found " << vendor_name << " accelerator: " << pcie_addr + << " (vendor=" << std::hex << vendor_id << ", device=" << device_id << ", class=" << class_id << std::dec << ")"; - num_aws_accel++; - num_nvidia_accel += is_nvidia_accel; + if (is_nvidia_accel) { + num_nvidia_accel++; + } else if (is_amd_accel) { + num_amd_accel++; + } else { + num_aws_accel++; + } } } - NIXL_TRACE << "Discovered " << num_aws_accel << " " - << vendor_names[num_aws_accel == num_nvidia_accel] << " devices via hwloc"; + NIXL_TRACE << "Discovered " << num_nvidia_accel << " NVIDIA, " + << num_amd_accel << " AMD, and " + << num_aws_accel << " Neuron accelerators via hwloc"; // If we found more than 8 NVIDIA accelerators on P5en, investigate further if (num_nvidia_accel > 8) { @@ -514,10 +531,10 @@ nixlLibfabricTopology::buildTopologyAwareGrouping() { NIXL_WARN << "Could not find hwloc object for PCIe address: " << pcie_addr; } } - // Step 2: Discover accelerators + // Step 2: Discover accelerators (NVIDIA and AMD) hwloc_obj_t pci_obj = nullptr; while ((pci_obj = hwloc_get_next_pcidev(hwloc_topology, pci_obj)) != nullptr) { - if (isNvidiaAccel(pci_obj)) { + if (isNvidiaAccel(pci_obj) || isAmdAccel(pci_obj)) { AccelInfo accel; accel.hwloc_node = pci_obj; accel.domain_id = pci_obj->attr->pcidev.domain; @@ -643,6 +660,52 @@ nixlLibfabricTopology::isNeuronAccel(hwloc_obj_t obj) const { obj->attr->pcidev.device_id) != std::end(NEURON_DEVICE_IDS); } +bool +nixlLibfabricTopology::isAmdAccel(hwloc_obj_t obj) const { + if (!obj || obj->type != HWLOC_OBJ_PCI_DEVICE) { + return false; + } + // AMD vendor ID is 0x1002 + if (obj->attr->pcidev.vendor_id != 0x1002) { + return false; + } + // AMD MI300x/MI355/MI455 device IDs + // MI300X: 0x74a0-0x74af range + // MI355/MI455: Will be added when device IDs are known + static const uint16_t AMD_GPU_DEVICE_IDS[] = { + 0x74a0, // MI300X + 0x74a1, // MI300X variant + 0x74a2, // MI300X variant + 0x74a3, // MI300X variant + 0x74a4, // MI300X variant + 0x74a5, // MI300X variant + 0x74a6, // MI300X variant + 0x74a7, // MI300X variant + 0x74a8, // MI300X variant + 0x74a9, // MI300X variant + 0x74aa, // MI300X variant + 0x74ab, // MI300X variant + 0x74ac, // MI300X variant + 0x74ad, // MI300X variant + 0x74ae, // MI300X variant + 0x74af, // MI300X variant + }; + + uint16_t device_id = obj->attr->pcidev.device_id; + + // Check if it's in the known device ID list + if (std::find(std::begin(AMD_GPU_DEVICE_IDS), + std::end(AMD_GPU_DEVICE_IDS), + device_id) != std::end(AMD_GPU_DEVICE_IDS)) { + return true; + } + + // Fallback: Check PCI class ID for display controller (GPU) + // Class 0x300-0x3ff for display controllers (similar to NVIDIA check) + uint16_t class_id = obj->attr->pcidev.class_id; + return (class_id >= 0x300 && class_id < 0x400); +} + bool nixlLibfabricTopology::isEfaDevice(hwloc_obj_t obj) const { if (!obj || obj->type != HWLOC_OBJ_PCI_DEVICE) { diff --git a/src/utils/libfabric/libfabric_topology.h b/src/utils/libfabric/libfabric_topology.h index 09dbeec1..9b1672b6 100644 --- a/src/utils/libfabric/libfabric_topology.h +++ b/src/utils/libfabric/libfabric_topology.h @@ -44,6 +44,7 @@ class nixlLibfabricTopology { // System information int num_aws_accel; // AWS Trainium accelerators int num_nvidia_accel; // NVIDIA GPU accelerators + int num_amd_accel; // AMD GPU accelerators (MI300x, MI355, MI455) int num_numa_nodes; int num_devices; @@ -122,6 +123,8 @@ class nixlLibfabricTopology { bool isNeuronAccel(hwloc_obj_t obj) const; bool + isAmdAccel(hwloc_obj_t obj) const; + bool isEfaDevice(hwloc_obj_t obj) const; public: @@ -143,6 +146,11 @@ class nixlLibfabricTopology { return num_nvidia_accel; } + int + getNumAmdAccel() const { + return num_amd_accel; + } + const std::vector & getAllDevices() const { return all_devices; @@ -164,7 +172,13 @@ class nixlLibfabricTopology { enum fi_hmem_iface getMrAttrIface(int device_id) const { - return (device_id < num_nvidia_accel) ? FI_HMEM_CUDA : FI_HMEM_NEURON; + if (device_id < num_nvidia_accel) { + return FI_HMEM_CUDA; + } else if (device_id < num_nvidia_accel + num_amd_accel) { + return FI_HMEM_ROCR; + } else { + return FI_HMEM_NEURON; + } } // Debug/info From 8fbe1adf40859a6b64bff2f342d820a0c348cb82 Mon Sep 17 00:00:00 2001 From: Matvei Pashkovskii Date: Fri, 27 Feb 2026 14:06:34 +0200 Subject: [PATCH 2/8] fix: Update AMD accelerator device ID list for MI300 and MI355 series --- src/utils/libfabric/libfabric_topology.cpp | 40 ++++++++++++---------- 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/src/utils/libfabric/libfabric_topology.cpp b/src/utils/libfabric/libfabric_topology.cpp index 0620dff3..c532001c 100644 --- a/src/utils/libfabric/libfabric_topology.cpp +++ b/src/utils/libfabric/libfabric_topology.cpp @@ -669,26 +669,28 @@ nixlLibfabricTopology::isAmdAccel(hwloc_obj_t obj) const { if (obj->attr->pcidev.vendor_id != 0x1002) { return false; } - // AMD MI300x/MI355/MI455 device IDs - // MI300X: 0x74a0-0x74af range - // MI355/MI455: Will be added when device IDs are known + // AMD Instinct MI300/MI355 series device IDs + // Sources: + // - https://github.com/GPUOpen-Tools/device_info/blob/master/DeviceInfo.cpp + // - https://github.com/openbsd/src/blob/master/sys/dev/pci/drm/amd/amdgpu/amdgpu_devlist.h + // - https://github.com/ROCm/k8s-device-plugin/issues/112 + // - https://github.com/ROCm/ROCm/issues/5891 + // Architecture: CDNA3 (gfx942) and CDNA4 (gfx950) static const uint16_t AMD_GPU_DEVICE_IDS[] = { - 0x74a0, // MI300X - 0x74a1, // MI300X variant - 0x74a2, // MI300X variant - 0x74a3, // MI300X variant - 0x74a4, // MI300X variant - 0x74a5, // MI300X variant - 0x74a6, // MI300X variant - 0x74a7, // MI300X variant - 0x74a8, // MI300X variant - 0x74a9, // MI300X variant - 0x74aa, // MI300X variant - 0x74ab, // MI300X variant - 0x74ac, // MI300X variant - 0x74ad, // MI300X variant - 0x74ae, // MI300X variant - 0x74af, // MI300X variant + // MI300 Series (CDNA3 - gfx942) + 0x74a0, // MI300A APU + 0x74a1, // MI300X dGPU (most common) + 0x74a2, // MI308X + 0x74a5, // MI325X + 0x74a9, // MI300XHF + 0x74b5, // MI300X VF (Virtual Function) + + // MI355 Series (CDNA4 - gfx950) + 0x75a0, // MI355X + 0x75a1, // MI355X variant + 0x75a3, // MI355X variant (Chip ID 30115) + + // Note: MI455X (CDNA5) device IDs not yet available (H2 2026 release) }; uint16_t device_id = obj->attr->pcidev.device_id; From 77e1225983f3e9be206b3db40b464df83239534c Mon Sep 17 00:00:00 2001 From: Matvei Pashkovskii Date: Mon, 2 Mar 2026 13:33:30 +0000 Subject: [PATCH 3/8] feat: Add HIP support for AMD accelerators in libfabric plugin and tests --- src/plugins/libfabric/libfabric_backend.h | 4 ++++ src/plugins/libfabric/meson.build | 12 ++++++++++-- src/utils/libfabric/libfabric_rail_manager.h | 4 ++++ src/utils/libfabric/libfabric_topology.cpp | 19 ++++++++++--------- src/utils/libfabric/meson.build | 18 +++++++++++++----- .../libfabric/libfabric_topology_test.cpp | 6 +++++- test/unit/utils/libfabric/meson.build | 10 +++++++++- 7 files changed, 55 insertions(+), 18 deletions(-) diff --git a/src/plugins/libfabric/libfabric_backend.h b/src/plugins/libfabric/libfabric_backend.h index 912e7255..2c218939 100644 --- a/src/plugins/libfabric/libfabric_backend.h +++ b/src/plugins/libfabric/libfabric_backend.h @@ -38,9 +38,13 @@ #include "libfabric/libfabric_common.h" #ifdef HAVE_CUDA +#ifdef __HIP_PLATFORM_AMD__ +#include +#else #include #include #endif +#endif // Forward declarations class nixlLibfabricEngine; diff --git a/src/plugins/libfabric/meson.build b/src/plugins/libfabric/meson.build index 1fdb6fb7..97cfa60f 100644 --- a/src/plugins/libfabric/meson.build +++ b/src/plugins/libfabric/meson.build @@ -16,6 +16,14 @@ # LibFabric plugin configuration +# Hipify sources that include cuda_runtime.h for ROCm/HIP builds +hipify_cmd = find_program('hipify-perl') +hipify_src = generator(hipify_cmd, + output : ['@BASENAME@_hip.cpp'], + arguments : ['@INPUT@', '@EXTRA_ARGS@', '@OUTPUT@']) + +libfabric_backend_hip_src = hipify_src.process('libfabric_backend.cpp', extra_args: '-o') + # Enable libfabric utils layer libfabric_plugin_deps = [ nixl_infra, @@ -38,7 +46,7 @@ endif if 'LIBFABRIC' in static_plugins libfabric_backend_lib = static_library( 'LIBFABRIC', - 'libfabric_backend.cpp', + libfabric_backend_hip_src, 'libfabric_backend.h', 'libfabric_plugin.cpp', dependencies: libfabric_plugin_deps, @@ -50,7 +58,7 @@ if 'LIBFABRIC' in static_plugins else libfabric_backend_lib = shared_library( 'LIBFABRIC', - 'libfabric_backend.cpp', + libfabric_backend_hip_src, 'libfabric_backend.h', 'libfabric_plugin.cpp', dependencies: libfabric_plugin_deps, diff --git a/src/utils/libfabric/libfabric_rail_manager.h b/src/utils/libfabric/libfabric_rail_manager.h index b2294170..150d0897 100644 --- a/src/utils/libfabric/libfabric_rail_manager.h +++ b/src/utils/libfabric/libfabric_rail_manager.h @@ -28,9 +28,13 @@ #include "libfabric_rail.h" #ifdef HAVE_CUDA +#ifdef __HIP_PLATFORM_AMD__ +#include +#else #include #include #endif +#endif // Forward declarations class nixlLibfabricTopology; diff --git a/src/utils/libfabric/libfabric_topology.cpp b/src/utils/libfabric/libfabric_topology.cpp index c532001c..7ef5264c 100644 --- a/src/utils/libfabric/libfabric_topology.cpp +++ b/src/utils/libfabric/libfabric_topology.cpp @@ -29,8 +29,12 @@ #include #ifdef HAVE_CUDA +#ifdef __HIP_PLATFORM_AMD__ +#include +#else #include #endif +#endif nixlLibfabricTopology::nixlLibfabricTopology() : num_aws_accel(0), @@ -348,12 +352,11 @@ nixlLibfabricTopology::discoverAccelWithHwloc() { uint16_t device_id = pci_obj->attr->pcidev.device_id; uint16_t class_id = pci_obj->attr->pcidev.class_id; - const char *vendor_name = is_nvidia_accel ? "NVIDIA" : - is_amd_accel ? "AMD" : "NEURON"; + const char *vendor_name = is_nvidia_accel ? "NVIDIA" : is_amd_accel ? "AMD" : "NEURON"; NIXL_TRACE << "Found " << vendor_name << " accelerator: " << pcie_addr - << " (vendor=" << std::hex << vendor_id - << ", device=" << device_id << ", class=" << class_id << std::dec << ")"; + << " (vendor=" << std::hex << vendor_id << ", device=" << device_id + << ", class=" << class_id << std::dec << ")"; if (is_nvidia_accel) { num_nvidia_accel++; @@ -365,8 +368,7 @@ nixlLibfabricTopology::discoverAccelWithHwloc() { } } - NIXL_TRACE << "Discovered " << num_nvidia_accel << " NVIDIA, " - << num_amd_accel << " AMD, and " + NIXL_TRACE << "Discovered " << num_nvidia_accel << " NVIDIA, " << num_amd_accel << " AMD, and " << num_aws_accel << " Neuron accelerators via hwloc"; // If we found more than 8 NVIDIA accelerators on P5en, investigate further @@ -696,9 +698,8 @@ nixlLibfabricTopology::isAmdAccel(hwloc_obj_t obj) const { uint16_t device_id = obj->attr->pcidev.device_id; // Check if it's in the known device ID list - if (std::find(std::begin(AMD_GPU_DEVICE_IDS), - std::end(AMD_GPU_DEVICE_IDS), - device_id) != std::end(AMD_GPU_DEVICE_IDS)) { + if (std::find(std::begin(AMD_GPU_DEVICE_IDS), std::end(AMD_GPU_DEVICE_IDS), device_id) != + std::end(AMD_GPU_DEVICE_IDS)) { return true; } diff --git a/src/utils/libfabric/meson.build b/src/utils/libfabric/meson.build index 67eb3696..35d0d7a8 100644 --- a/src/utils/libfabric/meson.build +++ b/src/utils/libfabric/meson.build @@ -14,14 +14,22 @@ # See the License for the specific language governing permissions and # limitations under the License. +# Hipify sources that include cuda_runtime.h for ROCm/HIP builds +hipify_cmd = find_program('hipify-perl') +hipify_src = generator(hipify_cmd, + output : ['@BASENAME@_hip.cpp'], + arguments : ['@INPUT@', '@EXTRA_ARGS@', '@OUTPUT@']) + +libfabric_topology_hip_src = hipify_src.process('libfabric_topology.cpp', extra_args: '-o') +libfabric_rail_manager_hip_src = hipify_src.process('libfabric_rail_manager.cpp', extra_args: '-o') + # Source files -libfabric_utils_sources = files( +libfabric_utils_sources = [ 'libfabric_rail.cpp', - 'libfabric_rail_manager.cpp', 'libfabric_common.cpp', - 'libfabric_topology.cpp', - # More implementation files will be added as we create them -) + libfabric_topology_hip_src, + libfabric_rail_manager_hip_src, +] # Header files libfabric_utils_headers = files( diff --git a/test/unit/utils/libfabric/libfabric_topology_test.cpp b/test/unit/utils/libfabric/libfabric_topology_test.cpp index 6bb4cfe2..92840145 100644 --- a/test/unit/utils/libfabric/libfabric_topology_test.cpp +++ b/test/unit/utils/libfabric/libfabric_topology_test.cpp @@ -21,8 +21,12 @@ #include "common/nixl_log.h" #ifdef CUDA_FOUND +#ifdef __HIP_PLATFORM_AMD__ +#include +#else #include #endif +#endif int main() { @@ -47,7 +51,7 @@ main() { #ifdef CUDA_FOUND // Get PCI bus ID for this GPU cudaDeviceProp prop; - cudaGetDeviceProperties(&prop, gpu_id); + (void)cudaGetDeviceProperties(&prop, gpu_id); char pci_bus_id[32]; snprintf(pci_bus_id, diff --git a/test/unit/utils/libfabric/meson.build b/test/unit/utils/libfabric/meson.build index 85f8528b..e47810b5 100644 --- a/test/unit/utils/libfabric/meson.build +++ b/test/unit/utils/libfabric/meson.build @@ -14,6 +14,14 @@ # See the License for the specific language governing permissions and # limitations under the License. +# Hipify sources that include cuda_runtime.h for ROCm/HIP builds +hipify_cmd = find_program('hipify-perl') +hipify_src = generator(hipify_cmd, + output : ['@BASENAME@_hip.cpp'], + arguments : ['@INPUT@', '@EXTRA_ARGS@', '@OUTPUT@']) + +libfabric_topology_test_hip_src = hipify_src.process('libfabric_topology_test.cpp', extra_args: '-o') + libfabric_utils_dep = [ libfabric_dep, nixl_common_deps ] libfabric_test_cpp_args = [] @@ -25,7 +33,7 @@ endif if get_option('buildtype') != 'release' libfabric_topology_test_bin = executable('libfabric_topology_test', - 'libfabric_topology_test.cpp', + libfabric_topology_test_hip_src, dependencies: libfabric_utils_dep, include_directories: [nixl_inc_dirs, utils_inc_dirs], link_with: libfabric_utils_lib, From 1937abd73ec88e9be4f46f14fe324158db3dfc36 Mon Sep 17 00:00:00 2001 From: Matvei Pashkovskii Date: Fri, 6 Mar 2026 10:13:27 +0000 Subject: [PATCH 4/8] fix: add CUcontext/CUdevice AMD mapping --- src/plugins/libfabric/libfabric_backend.h | 4 ++ .../libfabric/libfabric_rail_manager.cpp | 4 ++ src/utils/libfabric/libfabric_topology.cpp | 39 ++----------------- src/utils/libfabric/libfabric_topology.h | 2 +- 4 files changed, 13 insertions(+), 36 deletions(-) diff --git a/src/plugins/libfabric/libfabric_backend.h b/src/plugins/libfabric/libfabric_backend.h index 2c218939..d153e72a 100644 --- a/src/plugins/libfabric/libfabric_backend.h +++ b/src/plugins/libfabric/libfabric_backend.h @@ -40,6 +40,10 @@ #ifdef HAVE_CUDA #ifdef __HIP_PLATFORM_AMD__ #include +#include +// Define CUDA types as HIP equivalents for AMD +typedef hipCtx_t CUcontext; +typedef hipDevice_t CUdevice; #else #include #include diff --git a/src/utils/libfabric/libfabric_rail_manager.cpp b/src/utils/libfabric/libfabric_rail_manager.cpp index 7d9b9c04..2edb19aa 100644 --- a/src/utils/libfabric/libfabric_rail_manager.cpp +++ b/src/utils/libfabric/libfabric_rail_manager.cpp @@ -51,6 +51,10 @@ nixlLibfabricRailManager::nixlLibfabricRailManager(size_t striping_threshold) runtime_ = FI_HMEM_CUDA; NIXL_INFO << "System runtime: CUDA for " << topology->getNumNvidiaAccel() << " NVIDIA GPU(s)"; + } else if (topology->getNumAmdAccel() > 0) { + runtime_ = FI_HMEM_ROCR; + NIXL_INFO << "System runtime: ROCr for " << topology->getNumAmdAccel() + << " AMD GPU(s)"; } else if (topology->getNumAwsAccel() > 0) { runtime_ = FI_HMEM_NEURON; NIXL_INFO << "System runtime: NEURON for " << topology->getNumAwsAccel() diff --git a/src/utils/libfabric/libfabric_topology.cpp b/src/utils/libfabric/libfabric_topology.cpp index 7ef5264c..f5e991b2 100644 --- a/src/utils/libfabric/libfabric_topology.cpp +++ b/src/utils/libfabric/libfabric_topology.cpp @@ -671,42 +671,11 @@ nixlLibfabricTopology::isAmdAccel(hwloc_obj_t obj) const { if (obj->attr->pcidev.vendor_id != 0x1002) { return false; } - // AMD Instinct MI300/MI355 series device IDs - // Sources: - // - https://github.com/GPUOpen-Tools/device_info/blob/master/DeviceInfo.cpp - // - https://github.com/openbsd/src/blob/master/sys/dev/pci/drm/amd/amdgpu/amdgpu_devlist.h - // - https://github.com/ROCm/k8s-device-plugin/issues/112 - // - https://github.com/ROCm/ROCm/issues/5891 - // Architecture: CDNA3 (gfx942) and CDNA4 (gfx950) - static const uint16_t AMD_GPU_DEVICE_IDS[] = { - // MI300 Series (CDNA3 - gfx942) - 0x74a0, // MI300A APU - 0x74a1, // MI300X dGPU (most common) - 0x74a2, // MI308X - 0x74a5, // MI325X - 0x74a9, // MI300XHF - 0x74b5, // MI300X VF (Virtual Function) - - // MI355 Series (CDNA4 - gfx950) - 0x75a0, // MI355X - 0x75a1, // MI355X variant - 0x75a3, // MI355X variant (Chip ID 30115) - - // Note: MI455X (CDNA5) device IDs not yet available (H2 2026 release) - }; - - uint16_t device_id = obj->attr->pcidev.device_id; - - // Check if it's in the known device ID list - if (std::find(std::begin(AMD_GPU_DEVICE_IDS), std::end(AMD_GPU_DEVICE_IDS), device_id) != - std::end(AMD_GPU_DEVICE_IDS)) { - return true; - } - - // Fallback: Check PCI class ID for display controller (GPU) - // Class 0x300-0x3ff for display controllers (similar to NVIDIA check) + // Only count devices with GPU class (0x300-0x3ff for display controllers) + // Class 0x302 is 3D controller (GPU), 0x680 is other devices (network, etc.) + // MI300X uses class 0x1200 (Processing accelerators), consumer GPUs use 0x300-0x3ff uint16_t class_id = obj->attr->pcidev.class_id; - return (class_id >= 0x300 && class_id < 0x400); + return (class_id >= 0x300 && class_id < 0x400) || (class_id == 0x1200); } bool diff --git a/src/utils/libfabric/libfabric_topology.h b/src/utils/libfabric/libfabric_topology.h index 9b1672b6..78abc941 100644 --- a/src/utils/libfabric/libfabric_topology.h +++ b/src/utils/libfabric/libfabric_topology.h @@ -44,7 +44,7 @@ class nixlLibfabricTopology { // System information int num_aws_accel; // AWS Trainium accelerators int num_nvidia_accel; // NVIDIA GPU accelerators - int num_amd_accel; // AMD GPU accelerators (MI300x, MI355, MI455) + int num_amd_accel; // AMD GPU accelerators int num_numa_nodes; int num_devices; From fb4af618f96bcdd110e8e055a4fbfc3bc17c000b Mon Sep 17 00:00:00 2001 From: Matvei Pashkovskii Date: Thu, 12 Mar 2026 13:43:31 +0000 Subject: [PATCH 5/8] feat: support AMD ROCm runtime in memory registration --- src/plugins/libfabric/libfabric_backend.cpp | 2 +- src/utils/libfabric/libfabric_rail_manager.cpp | 3 +-- subprojects/.wraplock | 0 3 files changed, 2 insertions(+), 3 deletions(-) create mode 100644 subprojects/.wraplock diff --git a/src/plugins/libfabric/libfabric_backend.cpp b/src/plugins/libfabric/libfabric_backend.cpp index 2998cc82..31ba55a6 100644 --- a/src/plugins/libfabric/libfabric_backend.cpp +++ b/src/plugins/libfabric/libfabric_backend.cpp @@ -727,7 +727,7 @@ nixlLibfabricEngine::registerMem(const nixlBlobDesc &mem, // Use system runtime type to determine device-specific operations if (nixl_mem == VRAM_SEG) { #ifdef HAVE_CUDA - if (runtime_ == FI_HMEM_CUDA) { + if (runtime_ == FI_HMEM_CUDA || runtime_ == FI_HMEM_ROCR) { // CUDA-specific address query // For multi-GPU support, skip CUDA address workaround if (cuda_addr_wa_) { diff --git a/src/utils/libfabric/libfabric_rail_manager.cpp b/src/utils/libfabric/libfabric_rail_manager.cpp index 2edb19aa..c37faed1 100644 --- a/src/utils/libfabric/libfabric_rail_manager.cpp +++ b/src/utils/libfabric/libfabric_rail_manager.cpp @@ -53,8 +53,7 @@ nixlLibfabricRailManager::nixlLibfabricRailManager(size_t striping_threshold) << " NVIDIA GPU(s)"; } else if (topology->getNumAmdAccel() > 0) { runtime_ = FI_HMEM_ROCR; - NIXL_INFO << "System runtime: ROCr for " << topology->getNumAmdAccel() - << " AMD GPU(s)"; + NIXL_INFO << "System runtime: ROCr for " << topology->getNumAmdAccel() << " AMD GPU(s)"; } else if (topology->getNumAwsAccel() > 0) { runtime_ = FI_HMEM_NEURON; NIXL_INFO << "System runtime: NEURON for " << topology->getNumAwsAccel() diff --git a/subprojects/.wraplock b/subprojects/.wraplock new file mode 100644 index 00000000..e69de29b From 48c5c65cb185f5b779c28853bfc3751005a274d7 Mon Sep 17 00:00:00 2001 From: Matvei Pashkovskii Date: Thu, 12 Mar 2026 15:57:28 +0000 Subject: [PATCH 6/8] feat: Implement AMD ROCr support for memory registration and topology discovery --- .gitignore | 5 +- src/plugins/libfabric/libfabric_backend.cpp | 140 ++++++++++++++++-- src/plugins/libfabric/libfabric_backend.h | 4 + src/utils/libfabric/libfabric_rail.cpp | 7 + .../libfabric/libfabric_rail_manager.cpp | 3 + src/utils/libfabric/libfabric_topology.cpp | 55 +++---- src/utils/libfabric/libfabric_topology.h | 2 +- .../libfabric/libfabric_topology_test.cpp | 2 +- 8 files changed, 165 insertions(+), 53 deletions(-) diff --git a/.gitignore b/.gitignore index d352dd75..31b5895e 100644 --- a/.gitignore +++ b/.gitignore @@ -20,4 +20,7 @@ cufile.log .cache/ # Asio -subprojects/asio-* \ No newline at end of file +subprojects/asio-* + +build +subprojects/.wraplock \ No newline at end of file diff --git a/src/plugins/libfabric/libfabric_backend.cpp b/src/plugins/libfabric/libfabric_backend.cpp index 2998cc82..90fb8fb1 100644 --- a/src/plugins/libfabric/libfabric_backend.cpp +++ b/src/plugins/libfabric/libfabric_backend.cpp @@ -76,6 +76,110 @@ nrtQueryAddr(const void *va, std::string *efa_bdf) { return -1; } +// ROCr (AMD GPU) runtime library loading +void * +dlopen_libhsa() { + // Try libhsa-runtime64.so first + static void *handle = dlopen("libhsa-runtime64.so.1", RTLD_NOW | RTLD_LAZY); + if (handle) { + return handle; + } + // Fallback to versioned library + handle = dlopen("libhsa-runtime64.so", RTLD_NOW | RTLD_LAZY); + return handle; +} + +void * +dlopen_libhip() { + // Try libamdhip64.so (HIP Runtime) as alternative + static void *handle = dlopen("libamdhip64.so.6", RTLD_NOW | RTLD_LAZY); + if (handle) { + return handle; + } + // Fallback to unversioned library + handle = dlopen("libamdhip64.so", RTLD_NOW | RTLD_LAZY); + return handle; +} + +template +Fn * +_load_hsa_symbol(const char *fn_name, Fn *) { + void *hsa_handle = dlopen_libhsa(); + if (hsa_handle) { + return reinterpret_cast(dlsym(hsa_handle, fn_name)); + } + return nullptr; +} + +template +Fn * +_load_hip_symbol(const char *fn_name, Fn *) { + void *hip_handle = dlopen_libhip(); + if (hip_handle) { + return reinterpret_cast(dlsym(hip_handle, fn_name)); + } + return nullptr; +} + +#define LOAD_HSA_SYMBOL(sym) _load_hsa_symbol(#sym, &sym) +#define LOAD_HIP_SYMBOL(sym) _load_hip_symbol(#sym, &sym) + +// HIP API function signatures for dynamic loading +using hipGetDeviceProperties_fn = int (*)(void *prop, int device); +using hipPointerGetAttribute_fn = int (*)(void *data, int attribute, const void *ptr); +using hipDeviceGetPCIBusId_fn = int (*)(char *pciBusId, int len, int device); + +// ROCr (AMD GPU) memory address query using HIP APIs +int +rocrQueryAddr(const void *va, std::string *efa_bdf) { + // Strategy: Use HIP runtime to query PCI bus ID from memory address + // HIP API: hipPointerGetAttribute -> get device ID -> hipDeviceGetPCIBusId + + // Load HIP symbols dynamically + hipPointerGetAttribute_fn hipPointerGetAttribute = nullptr; + hipDeviceGetPCIBusId_fn hipDeviceGetPCIBusId = nullptr; + + void *hip_handle = dlopen_libhip(); + if (hip_handle) { + hipPointerGetAttribute = reinterpret_cast( + dlsym(hip_handle, "hipPointerGetAttribute")); + hipDeviceGetPCIBusId = reinterpret_cast( + dlsym(hip_handle, "hipDeviceGetPCIBusId")); + } + + if (!hipPointerGetAttribute || !hipDeviceGetPCIBusId) { + // HIP library not available - this is acceptable, fall back to all rails + NIXL_TRACE << "HIP runtime library not available - using all rails for AMD GPU memory"; + return -1; + } + + // Query device ID from memory pointer + int device_id = -1; + // hipPointerAttribute_t::device = 2 + constexpr int hipPointerAttributeDevice = 2; + int ret = hipPointerGetAttribute(&device_id, hipPointerAttributeDevice, va); + if (ret != 0 || device_id < 0) { + NIXL_TRACE << "Failed to query device ID from memory address " << va + << " - using all rails"; + return -1; + } + + // Query PCI bus ID from device ID + char pci_bus_id[64]; + ret = hipDeviceGetPCIBusId(pci_bus_id, sizeof(pci_bus_id), device_id); + if (ret != 0) { + NIXL_TRACE << "Failed to query PCI bus ID for AMD GPU device " << device_id + << " - using all rails"; + return -1; + } + + // Format PCI bus ID (HIP returns format like "0000:59:00.0") + efa_bdf->assign(pci_bus_id); + NIXL_DEBUG << "ROCr query: memory " << va << " -> device " << device_id + << " -> PCI " << *efa_bdf; + return 0; +} + } // namespace #ifdef HAVE_CUDA @@ -301,6 +405,7 @@ nixlLibfabricEngine::nixlLibfabricEngine(const nixlBackendInitParams *init_param NIXL_INFO << "System runtime: " << (runtime_ == FI_HMEM_CUDA ? "CUDA" : + runtime_ == FI_HMEM_ROCR ? "ROCr" : runtime_ == FI_HMEM_NEURON ? "NEURON" : "SYSTEM"); @@ -727,8 +832,8 @@ nixlLibfabricEngine::registerMem(const nixlBlobDesc &mem, // Use system runtime type to determine device-specific operations if (nixl_mem == VRAM_SEG) { #ifdef HAVE_CUDA - if (runtime_ == FI_HMEM_CUDA) { - // CUDA-specific address query + if (runtime_ == FI_HMEM_CUDA || runtime_ == FI_HMEM_ROCR) { + // GPU-specific address query (CUDA or ROCr) // For multi-GPU support, skip CUDA address workaround if (cuda_addr_wa_) { bool need_restart; @@ -753,17 +858,28 @@ nixlLibfabricEngine::registerMem(const nixlBlobDesc &mem, } // Query PCI bus ID from memory address (AFTER setting context) - bool is_dev; - CUdevice dev; - CUcontext ctx; - - int ret = cudaQueryAddr((void *)mem.addr, is_dev, dev, ctx, pci_bus_id); - if (ret || !is_dev) { - NIXL_ERROR << "Failed to query device from memory " << (void *)mem.addr; - return NIXL_ERR_BACKEND; - } + if (runtime_ == FI_HMEM_CUDA) { + bool is_dev; + CUdevice dev; + CUcontext ctx; + + int ret = cudaQueryAddr((void *)mem.addr, is_dev, dev, ctx, pci_bus_id); + if (ret || !is_dev) { + NIXL_ERROR << "Failed to query device from memory " << (void *)mem.addr; + return NIXL_ERR_BACKEND; + } - NIXL_DEBUG << "Queried PCI bus ID: " << pci_bus_id << " for GPU " << mem.devId; + NIXL_DEBUG << "Queried PCI bus ID: " << pci_bus_id << " for GPU " << mem.devId; + } else if (runtime_ == FI_HMEM_ROCR) { + // AMD ROCr-specific address query + int ret = rocrQueryAddr((void *)mem.addr, &pci_bus_id); + if (ret) { + NIXL_ERROR << "Failed to query device from memory " << (void *)mem.addr; + return NIXL_ERR_BACKEND; + } + + NIXL_DEBUG << "Queried PCI bus ID: " << pci_bus_id << " for GPU " << mem.devId; + } } #endif if (runtime_ == FI_HMEM_NEURON) { diff --git a/src/plugins/libfabric/libfabric_backend.h b/src/plugins/libfabric/libfabric_backend.h index 2c218939..d153e72a 100644 --- a/src/plugins/libfabric/libfabric_backend.h +++ b/src/plugins/libfabric/libfabric_backend.h @@ -40,6 +40,10 @@ #ifdef HAVE_CUDA #ifdef __HIP_PLATFORM_AMD__ #include +#include +// Define CUDA types as HIP equivalents for AMD +typedef hipCtx_t CUcontext; +typedef hipDevice_t CUdevice; #else #include #include diff --git a/src/utils/libfabric/libfabric_rail.cpp b/src/utils/libfabric/libfabric_rail.cpp index 9b8a64c6..4311c041 100644 --- a/src/utils/libfabric/libfabric_rail.cpp +++ b/src/utils/libfabric/libfabric_rail.cpp @@ -1285,6 +1285,13 @@ nixlLibfabricRail::registerMemory(void *buffer, mr_attr.device.cuda = device_id; NIXL_DEBUG << "CUDA memory registration - iface: FI_HMEM_CUDA, device.cuda: " << device_id; + } else if (iface == FI_HMEM_ROCR) { + // AMD ROCr memory registration + // ROCr uses HSA agent handles for device identification + // The device_id corresponds to the GPU index (0-based) + mr_attr.device.rocr = device_id; + NIXL_DEBUG << "ROCr memory registration - iface: FI_HMEM_ROCR, device.rocr: " + << device_id; } else if (iface == FI_HMEM_NEURON) { /* * Store a sentinel; libfabric requires this to be initialized. diff --git a/src/utils/libfabric/libfabric_rail_manager.cpp b/src/utils/libfabric/libfabric_rail_manager.cpp index 7d9b9c04..c37faed1 100644 --- a/src/utils/libfabric/libfabric_rail_manager.cpp +++ b/src/utils/libfabric/libfabric_rail_manager.cpp @@ -51,6 +51,9 @@ nixlLibfabricRailManager::nixlLibfabricRailManager(size_t striping_threshold) runtime_ = FI_HMEM_CUDA; NIXL_INFO << "System runtime: CUDA for " << topology->getNumNvidiaAccel() << " NVIDIA GPU(s)"; + } else if (topology->getNumAmdAccel() > 0) { + runtime_ = FI_HMEM_ROCR; + NIXL_INFO << "System runtime: ROCr for " << topology->getNumAmdAccel() << " AMD GPU(s)"; } else if (topology->getNumAwsAccel() > 0) { runtime_ = FI_HMEM_NEURON; NIXL_INFO << "System runtime: NEURON for " << topology->getNumAwsAccel() diff --git a/src/utils/libfabric/libfabric_topology.cpp b/src/utils/libfabric/libfabric_topology.cpp index 7ef5264c..0626636f 100644 --- a/src/utils/libfabric/libfabric_topology.cpp +++ b/src/utils/libfabric/libfabric_topology.cpp @@ -104,10 +104,20 @@ nixlLibfabricTopology::discoverTopology() { NIXL_INFO << "Using simplified topology for " << provider_name << " devices (no topology mapping needed)"; - // Set basic values without hwloc discovery - num_aws_accel = 0; // TCP doesn't need accelerator topology - num_numa_nodes = 1; // Simple fallback + // Still discover GPUs even in simplified mode for GPU memory registration + status = initHwlocTopology(); + if (status == NIXL_SUCCESS) { + status = discoverAccelWithHwloc(); + if (status != NIXL_SUCCESS) { + NIXL_WARN << "GPU discovery failed in simplified topology mode"; + // Not a fatal error - continue without GPUs + } + cleanupHwlocTopology(); + } else { + NIXL_WARN << "hwloc initialization failed - no GPU detection available"; + } + num_numa_nodes = 1; // Simple fallback // For TCP/sockets devices, no accelerator-mapping required. NIXL_INFO << "TCP devices available globally - no accelerator-specific mapping required"; } @@ -671,42 +681,11 @@ nixlLibfabricTopology::isAmdAccel(hwloc_obj_t obj) const { if (obj->attr->pcidev.vendor_id != 0x1002) { return false; } - // AMD Instinct MI300/MI355 series device IDs - // Sources: - // - https://github.com/GPUOpen-Tools/device_info/blob/master/DeviceInfo.cpp - // - https://github.com/openbsd/src/blob/master/sys/dev/pci/drm/amd/amdgpu/amdgpu_devlist.h - // - https://github.com/ROCm/k8s-device-plugin/issues/112 - // - https://github.com/ROCm/ROCm/issues/5891 - // Architecture: CDNA3 (gfx942) and CDNA4 (gfx950) - static const uint16_t AMD_GPU_DEVICE_IDS[] = { - // MI300 Series (CDNA3 - gfx942) - 0x74a0, // MI300A APU - 0x74a1, // MI300X dGPU (most common) - 0x74a2, // MI308X - 0x74a5, // MI325X - 0x74a9, // MI300XHF - 0x74b5, // MI300X VF (Virtual Function) - - // MI355 Series (CDNA4 - gfx950) - 0x75a0, // MI355X - 0x75a1, // MI355X variant - 0x75a3, // MI355X variant (Chip ID 30115) - - // Note: MI455X (CDNA5) device IDs not yet available (H2 2026 release) - }; - - uint16_t device_id = obj->attr->pcidev.device_id; - - // Check if it's in the known device ID list - if (std::find(std::begin(AMD_GPU_DEVICE_IDS), std::end(AMD_GPU_DEVICE_IDS), device_id) != - std::end(AMD_GPU_DEVICE_IDS)) { - return true; - } - - // Fallback: Check PCI class ID for display controller (GPU) - // Class 0x300-0x3ff for display controllers (similar to NVIDIA check) + // Only count devices with GPU class (0x300-0x3ff for display controllers) + // Class 0x302 is 3D controller (GPU), 0x680 is other devices (network, etc.) + // MI300X uses class 0x1200 (Processing accelerators), consumer GPUs use 0x300-0x3ff uint16_t class_id = obj->attr->pcidev.class_id; - return (class_id >= 0x300 && class_id < 0x400); + return (class_id >= 0x300 && class_id < 0x400) || (class_id == 0x1200); } bool diff --git a/src/utils/libfabric/libfabric_topology.h b/src/utils/libfabric/libfabric_topology.h index 9b1672b6..78abc941 100644 --- a/src/utils/libfabric/libfabric_topology.h +++ b/src/utils/libfabric/libfabric_topology.h @@ -44,7 +44,7 @@ class nixlLibfabricTopology { // System information int num_aws_accel; // AWS Trainium accelerators int num_nvidia_accel; // NVIDIA GPU accelerators - int num_amd_accel; // AMD GPU accelerators (MI300x, MI355, MI455) + int num_amd_accel; // AMD GPU accelerators int num_numa_nodes; int num_devices; diff --git a/test/unit/utils/libfabric/libfabric_topology_test.cpp b/test/unit/utils/libfabric/libfabric_topology_test.cpp index 92840145..04cc3e32 100644 --- a/test/unit/utils/libfabric/libfabric_topology_test.cpp +++ b/test/unit/utils/libfabric/libfabric_topology_test.cpp @@ -43,7 +43,7 @@ main() { topology.printTopologyInfo(); // Test GPU-specific queries only if GPUs are detected - int num_gpus = topology.getNumNvidiaAccel(); + int num_gpus = topology.getNumNvidiaAccel() + topology.getNumAmdAccel(); if (num_gpus > 0) { NIXL_INFO << "3. Testing GPU-specific queries (detected " << num_gpus << " GPUs)..."; int test_gpus = std::min(num_gpus, 3); // Test up to 3 GPUs or all available From 626c3af5b6eb6cbbf32a3fd7c696dd468cf9056a Mon Sep 17 00:00:00 2001 From: Matvei Pashkovskii Date: Fri, 13 Mar 2026 10:52:55 +0000 Subject: [PATCH 7/8] fix: remove duplicated HIP functionality --- examples/python/expanded_two_peers.py | 23 +++- src/plugins/libfabric/libfabric_backend.cpp | 137 ++------------------ src/utils/libfabric/libfabric_topology.cpp | 16 +-- 3 files changed, 34 insertions(+), 142 deletions(-) diff --git a/examples/python/expanded_two_peers.py b/examples/python/expanded_two_peers.py index 2ac4bce2..aaebfdb0 100755 --- a/examples/python/expanded_two_peers.py +++ b/examples/python/expanded_two_peers.py @@ -6,14 +6,27 @@ import argparse import pickle import random +import sys import numpy as np import torch -from nixl._api import nixl_agent, nixl_agent_config -from nixl.logging import get_logger +try: + try: + from nixl._api import nixl_agent, nixl_agent_config + from nixl.logging import get_logger + except ImportError: + from rixl._api import nixl_agent, nixl_agent_config + from rixl.logging import get_logger + + logger = get_logger(__name__) + NIXL_AVAILABLE = True +except ImportError: + import logging -logger = get_logger(__name__) + logger = logging.getLogger(__name__) + logger.error("NIXL API missing install NIXL.") + NIXL_AVAILABLE = False def parse_args(): @@ -32,6 +45,10 @@ def parse_args(): if __name__ == "__main__": + if not NIXL_AVAILABLE: + logger.warning("Skipping example - NIXL bindings not available") + sys.exit(0) + args = parse_args() # initiator use default port diff --git a/src/plugins/libfabric/libfabric_backend.cpp b/src/plugins/libfabric/libfabric_backend.cpp index 90fb8fb1..bac6b2bb 100644 --- a/src/plugins/libfabric/libfabric_backend.cpp +++ b/src/plugins/libfabric/libfabric_backend.cpp @@ -76,110 +76,6 @@ nrtQueryAddr(const void *va, std::string *efa_bdf) { return -1; } -// ROCr (AMD GPU) runtime library loading -void * -dlopen_libhsa() { - // Try libhsa-runtime64.so first - static void *handle = dlopen("libhsa-runtime64.so.1", RTLD_NOW | RTLD_LAZY); - if (handle) { - return handle; - } - // Fallback to versioned library - handle = dlopen("libhsa-runtime64.so", RTLD_NOW | RTLD_LAZY); - return handle; -} - -void * -dlopen_libhip() { - // Try libamdhip64.so (HIP Runtime) as alternative - static void *handle = dlopen("libamdhip64.so.6", RTLD_NOW | RTLD_LAZY); - if (handle) { - return handle; - } - // Fallback to unversioned library - handle = dlopen("libamdhip64.so", RTLD_NOW | RTLD_LAZY); - return handle; -} - -template -Fn * -_load_hsa_symbol(const char *fn_name, Fn *) { - void *hsa_handle = dlopen_libhsa(); - if (hsa_handle) { - return reinterpret_cast(dlsym(hsa_handle, fn_name)); - } - return nullptr; -} - -template -Fn * -_load_hip_symbol(const char *fn_name, Fn *) { - void *hip_handle = dlopen_libhip(); - if (hip_handle) { - return reinterpret_cast(dlsym(hip_handle, fn_name)); - } - return nullptr; -} - -#define LOAD_HSA_SYMBOL(sym) _load_hsa_symbol(#sym, &sym) -#define LOAD_HIP_SYMBOL(sym) _load_hip_symbol(#sym, &sym) - -// HIP API function signatures for dynamic loading -using hipGetDeviceProperties_fn = int (*)(void *prop, int device); -using hipPointerGetAttribute_fn = int (*)(void *data, int attribute, const void *ptr); -using hipDeviceGetPCIBusId_fn = int (*)(char *pciBusId, int len, int device); - -// ROCr (AMD GPU) memory address query using HIP APIs -int -rocrQueryAddr(const void *va, std::string *efa_bdf) { - // Strategy: Use HIP runtime to query PCI bus ID from memory address - // HIP API: hipPointerGetAttribute -> get device ID -> hipDeviceGetPCIBusId - - // Load HIP symbols dynamically - hipPointerGetAttribute_fn hipPointerGetAttribute = nullptr; - hipDeviceGetPCIBusId_fn hipDeviceGetPCIBusId = nullptr; - - void *hip_handle = dlopen_libhip(); - if (hip_handle) { - hipPointerGetAttribute = reinterpret_cast( - dlsym(hip_handle, "hipPointerGetAttribute")); - hipDeviceGetPCIBusId = reinterpret_cast( - dlsym(hip_handle, "hipDeviceGetPCIBusId")); - } - - if (!hipPointerGetAttribute || !hipDeviceGetPCIBusId) { - // HIP library not available - this is acceptable, fall back to all rails - NIXL_TRACE << "HIP runtime library not available - using all rails for AMD GPU memory"; - return -1; - } - - // Query device ID from memory pointer - int device_id = -1; - // hipPointerAttribute_t::device = 2 - constexpr int hipPointerAttributeDevice = 2; - int ret = hipPointerGetAttribute(&device_id, hipPointerAttributeDevice, va); - if (ret != 0 || device_id < 0) { - NIXL_TRACE << "Failed to query device ID from memory address " << va - << " - using all rails"; - return -1; - } - - // Query PCI bus ID from device ID - char pci_bus_id[64]; - ret = hipDeviceGetPCIBusId(pci_bus_id, sizeof(pci_bus_id), device_id); - if (ret != 0) { - NIXL_TRACE << "Failed to query PCI bus ID for AMD GPU device " << device_id - << " - using all rails"; - return -1; - } - - // Format PCI bus ID (HIP returns format like "0000:59:00.0") - efa_bdf->assign(pci_bus_id); - NIXL_DEBUG << "ROCr query: memory " << va << " -> device " << device_id - << " -> PCI " << *efa_bdf; - return 0; -} - } // namespace #ifdef HAVE_CUDA @@ -833,7 +729,7 @@ nixlLibfabricEngine::registerMem(const nixlBlobDesc &mem, if (nixl_mem == VRAM_SEG) { #ifdef HAVE_CUDA if (runtime_ == FI_HMEM_CUDA || runtime_ == FI_HMEM_ROCR) { - // GPU-specific address query (CUDA or ROCr) + // CUDA-specific address query // For multi-GPU support, skip CUDA address workaround if (cuda_addr_wa_) { bool need_restart; @@ -858,28 +754,17 @@ nixlLibfabricEngine::registerMem(const nixlBlobDesc &mem, } // Query PCI bus ID from memory address (AFTER setting context) - if (runtime_ == FI_HMEM_CUDA) { - bool is_dev; - CUdevice dev; - CUcontext ctx; - - int ret = cudaQueryAddr((void *)mem.addr, is_dev, dev, ctx, pci_bus_id); - if (ret || !is_dev) { - NIXL_ERROR << "Failed to query device from memory " << (void *)mem.addr; - return NIXL_ERR_BACKEND; - } - - NIXL_DEBUG << "Queried PCI bus ID: " << pci_bus_id << " for GPU " << mem.devId; - } else if (runtime_ == FI_HMEM_ROCR) { - // AMD ROCr-specific address query - int ret = rocrQueryAddr((void *)mem.addr, &pci_bus_id); - if (ret) { - NIXL_ERROR << "Failed to query device from memory " << (void *)mem.addr; - return NIXL_ERR_BACKEND; - } - - NIXL_DEBUG << "Queried PCI bus ID: " << pci_bus_id << " for GPU " << mem.devId; + bool is_dev; + CUdevice dev; + CUcontext ctx; + + int ret = cudaQueryAddr((void *)mem.addr, is_dev, dev, ctx, pci_bus_id); + if (ret || !is_dev) { + NIXL_ERROR << "Failed to query device from memory " << (void *)mem.addr; + return NIXL_ERR_BACKEND; } + + NIXL_DEBUG << "Queried PCI bus ID: " << pci_bus_id << " for GPU " << mem.devId; } #endif if (runtime_ == FI_HMEM_NEURON) { diff --git a/src/utils/libfabric/libfabric_topology.cpp b/src/utils/libfabric/libfabric_topology.cpp index 0626636f..f5e991b2 100644 --- a/src/utils/libfabric/libfabric_topology.cpp +++ b/src/utils/libfabric/libfabric_topology.cpp @@ -104,20 +104,10 @@ nixlLibfabricTopology::discoverTopology() { NIXL_INFO << "Using simplified topology for " << provider_name << " devices (no topology mapping needed)"; - // Still discover GPUs even in simplified mode for GPU memory registration - status = initHwlocTopology(); - if (status == NIXL_SUCCESS) { - status = discoverAccelWithHwloc(); - if (status != NIXL_SUCCESS) { - NIXL_WARN << "GPU discovery failed in simplified topology mode"; - // Not a fatal error - continue without GPUs - } - cleanupHwlocTopology(); - } else { - NIXL_WARN << "hwloc initialization failed - no GPU detection available"; - } - + // Set basic values without hwloc discovery + num_aws_accel = 0; // TCP doesn't need accelerator topology num_numa_nodes = 1; // Simple fallback + // For TCP/sockets devices, no accelerator-mapping required. NIXL_INFO << "TCP devices available globally - no accelerator-specific mapping required"; } From d5fcb0afc2eb9c7143d6d8a3e6a335b6ad57b095 Mon Sep 17 00:00:00 2001 From: Matvei Pashkovskii Date: Tue, 17 Mar 2026 13:34:21 +0200 Subject: [PATCH 8/8] feat: enhance libfabric support for CUDA and ROCr --- src/plugins/libfabric/libfabric_backend.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/plugins/libfabric/libfabric_backend.cpp b/src/plugins/libfabric/libfabric_backend.cpp index fc568543..515a6113 100644 --- a/src/plugins/libfabric/libfabric_backend.cpp +++ b/src/plugins/libfabric/libfabric_backend.cpp @@ -312,7 +312,7 @@ nixlLibfabricEngine::nixlLibfabricEngine(const nixlBackendInitParams *init_param "SYSTEM"); #ifdef HAVE_CUDA - if (runtime_ == FI_HMEM_CUDA) { + if (runtime_ == FI_HMEM_CUDA || runtime_ == FI_HMEM_ROCR) { // Initialize CUDA context management vramInitCtx(); // CUDA address workaround @@ -670,7 +670,7 @@ nixlLibfabricEngine::getSupportedMems() const { nixl_mem_list_t mems; mems.push_back(DRAM_SEG); #ifdef HAVE_CUDA - if (runtime_ == FI_HMEM_CUDA) { + if (runtime_ == FI_HMEM_CUDA || runtime_ == FI_HMEM_ROCR) { NIXL_DEBUG << "CUDA runtime detected, adding VRAM support"; mems.push_back(VRAM_SEG); } else { @@ -759,7 +759,7 @@ nixlLibfabricEngine::registerMem(const nixlBlobDesc &mem, #ifdef HAVE_CUDA // Set CUDA context before libfabric operations for VRAM - if (nixl_mem == VRAM_SEG && runtime_ == FI_HMEM_CUDA) { + if (nixl_mem == VRAM_SEG && (runtime_ == FI_HMEM_CUDA || runtime_ == FI_HMEM_ROCR)) { vramApplyCtx(); } #endif