This is an overlapping sequence detector implemented using verilog language. State Table : Current State Next State(in = 0, in = 1) Output(in = 0, in = 1) S0 S0, S1 0, 0 S1 S0, S2 0, 0 S2 S3, S2 0, 0 S3 S4, S2 0, 0 S4 S0, S1 0, 1