[FEAT|CPU|ISA] Implement SBCS Instruction

[begeistert]

Is your feature request related to a problem? Please describe.

Multi-word arithmetic (64-bit or larger integers) is currently impossible. The SBCS instruction is critical for propagating borrow bits across multiple 32-bit words.

Describe the solution you'd like

Implement SBCS in ArithmeticOps.cs. This instruction uses the existing Carry flag from the CPSR/APSR to perform the subtraction.
The operation is defined as: $Rd = Rn - Operand2 - \text{NOT}(Carry)$.

Acceptance Criteria

• Implement SBCS logic using the current Carry flag state.
• Correctly handle the "Not Carry" logic (ARM uses inverted carry for borrow).
• Ensure flags ($N, Z, C, V$) are updated after execution.
• Map the instruction in InstructionDecoder.cs.
• Passes unit tests, specifically chaining a SUBS followed by an SBCS.

Datasheet Reference

• ARMv6-M Architecture Reference Manual: Section A6.7.58 (SBCS)