[FEAT|CPU|ISA] Implement SUB and SUBS Instructions

[begeistert]

Is your feature request related to a problem? Please describe.

The CPU lacks basic integer subtraction capabilities. Without SUB and SUBS, the emulator cannot perform fundamental arithmetic operations, loop decrements, or comparisons. Specifically, SUBS is required to update the APSR flags used for conditional branching.

Describe the solution you'd like

Implement the logic for SUB (Subtract without flags) and SUBS (Subtract with flags) in ArithmeticOps.cs.
The operation is defined as: $Rd = Rn - Operand2$.

Acceptance Criteria:

• Implement SUB logic (Result calculation only).
• Implement SUBS logic (Result calculation + Flag updates).
• Ensure SUBS updates flags correctly:
  • N: Result is negative (bit 31).
  • Z: Result is zero.
  • C: Carry flag (Set to 1 if no borrow occurred).
  • V: Signed overflow.
• Map both instructions in InstructionDecoder.cs.
• Passes unit tests for immediate and register variants.

Datasheet Reference

• ARMv6-M Architecture Reference Manual:
  • Section A6.7.68 (SUB - immediate)
  • Section A6.7.69 (SUB - register)