[ndf]: define GPR predicates for TCMP/TSEL and eight-GPR P2R materialization

[XrXie]

Baseline commit

564ac2d8d868c441a8dc5e5f4d44efa7533a911d

This is a DESIGN-only architecture-decision request. It deliberately revises the current packed-predicate-Tile operand contract of TCMP/TSEL. It does not authorize ASL edits, encoding allocation, a branch, a pull request, release validation, tagging, or publication.

Related accepted contracts and decisions:

• current TCMP and TSEL packed-predicate semantics to be revised by this decision: PTO-TCMP-CONTRACT-001, PTO-TSEL-CONTRACT-001, ADR-0080;
• persistent 128-byte CUBE CellReg geometry: PTO-CUBE-CELL-STATE-001, [ndf]: define persistent Local CUBE CELL state and geometry #102;
• HiF4X2 group-64 raw-U32 scale words and Local CUBE_M32 scale layout: PTO-CUBE-HIF4-SCALE-001, PTO-CUBE-MATRIX-SCALE-CELL-001, ADR-0101 / [ndf]: define Matrix scale CELL layouts and per-row accumulator C scaling #136;
• current GPR binder capacity: PTO-B-IOR-BINDING-001.

Repository issue search at this baseline found no existing P2R issue.

Affected NDF clause IDs

• Proposed: PTO-P2R-PREDICATE-MATERIALIZATION-001
• Proposed: PTO-GPR-PREDICATE-PLANE-001
• Proposed: PTO-INST-TILE-P2R
• PTO-TCMP-CONTRACT-001
• PTO-TSEL-CONTRACT-001
• PTO-B-IOR-BINDING-001
• PTO-CUBE-CELL-STATE-001
• PTO-CUBE-MATRIX-SCALE-CELL-001
• PTO-CUBE-HIF4-SCALE-001

APPLY must discover every direct schema, descriptor, dispatch, legality, execution, catalog, decoder, documentation, AVS, and release-evidence owner after the architecture surface and encoding are frozen.

Normative delta

Replace the current packed Local predicate Tile at the TCMP/TSEL interface with ordered architectural 32-bit GPR predicate planes. These are ordinary architectural GPR operands, not an implementation-private predicate file and not slices hidden behind a predicate Tile descriptor.

Predicate GPRs are ordered first by logical Cell and then by the layout-defined element slot within that Cell. Let B(L) be the number of logical row/lane positions represented in each predicate GPR for layout L:

B(CUBE_M32) = 32
B(CUBE_M16) = 16

For DataType carrier width W and one 128-byte CellReg, the number of predicate GPRs produced or consumed per Cell is:

planes_per_cell(L, W) = 1024 / (B(L) * W)

Therefore:

Layout	32-bit type	16-bit type	8-bit type	Valid bits in each GPR
CUBE_M32	1	2	4	31:0
CUBE_M16	2	4	8	15:0

For Cell c, slot s, and logical row/lane r, the mapping is:

P[c,s][r] = compare(src_left.element(c,r,s), src_right.element(c,r,s))

element(c,r,s) is the ordinary layout accessor; s increases in logical low-column/low-subelement order and must not be inferred from bank, port, endianness, or writeback order. The architectural GPR sequence is:

Cell0.slot0, Cell0.slot1, ...,
Cell1.slot0, Cell1.slot1, ...,
...

The operation is not restricted to one CellReg. For C Cells it produces or consumes C * planes_per_cell(L,W) ordered GPRs. TCMP requires that many distinct writable GPR destinations; if the architectural GPR namespace or selected encoding cannot name the complete list, legality preflight rejects before any destination is written. Software must split the Tile into smaller operations. TSEL requires the same number and order of GPR sources; source GPRs may repeat and the architectural zero GPR supplies a zero plane.

For an M32 FP16 Cell this freezes:

P0[r] = compare(src_left.lane[r].bits[15:0],  src_right.lane[r].bits[15:0])
P1[r] = compare(src_left.lane[r].bits[31:16], src_right.lane[r].bits[31:16])

Thus one M32 FP16x2 TCMP Cell writes exactly two GPR results, in low-half then high-half order. TSEL reads the same two ordered GPRs and applies:

dst.lane[r].bits[15:0]  = P0[r] ? src_true.lane[r].bits[15:0]
                                  : src_false.lane[r].bits[15:0]
dst.lane[r].bits[31:16] = P1[r] ? src_true.lane[r].bits[31:16]
                                  : src_false.lane[r].bits[31:16]

For M16 only GPR bits 15:0 correspond to logical rows. GPR bits 31:16 never name extra M16 rows. Likewise, bits outside the valid rows of a tail Cell are predicate padding rather than valid results. TCMP applies its existing PadValue value contract to all such padding bits: Zero and Min write zero, Max writes one, and Null leaves the bit value architecturally unspecified. TSEL consumes only bits corresponding to valid data elements and never treats padding bits as additional rows. Scalar code may observe or overwrite the complete raw GPR, including such non-predicate padding bits.

TCMP comparison relations, floating special-value behavior, source snapshot rules, and numeric-status publication remain as in PTO-TCMP-CONTRACT-001. All GPR results of one accepted TCMP publish atomically after complete preflight. TSEL remains an exact raw-carrier select with zero selecting the false source and one selecting the true source.

These GPRs are in the ordinary architectural scalar-GPR namespace. Scalar instructions may read a TCMP result, write a later TSEL/P2R source, and otherwise use the same registers under the normal GPR ordering and dependency rules. There is no separate architecturally hidden predicate namespace.

Define P2R as a value operation with exactly eight ordered architectural 32-bit GPR sources P0..P7 and one new Local CellReg destination. Its result is:

for r in 0..31:
    D[r, byte_offset] = sum(((Pb >> r) & 1) << b, b=0..7)

equivalently:
    D[r, byte_offset][b] = Pb[r]

byte_offset is an unsigned U8-column offset in the range 0..3; values outside that range are illegal. If the offset operand/attribute is omitted, it defaults to zero. This behavior is equivalent to the existing ByteId0..ByteId3 value domain, but this issue does not require a particular encoding carrier for it.

The architectural bit mapping is fixed: source GPR Pb always supplies output bit b, and GPR bit r always supplies M32 lane/row r. P2R always consumes all 32 bits of every source GPR, independently of whether a source value was originally produced by an M16 or M32 TCMP. Sources may repeat. An explicitly named architectural zero GPR supplies an all-zero plane; omission of any of the eight sources is illegal.

P2R publishes one new Local CUBE_M32 U8 offset-column result over all 32 rows. In every physical lane, only byte/column byte_offset is valid and defined by the transpose above; the other three bytes/columns are Null padding and architecturally undefined. P2R has no merge source, never reads an old destination, and performs no hidden U8-to-HiF4 reinterpretation. All eight GPR sources and the offset are snapshotted before destination publication. The selected-byte payload, Null definedness of every unselected byte, and destination descriptor publish atomically; rejection publishes none. The operation performs no memory access, rounding, saturation, conversion, floating-status update, or implicit numeric interpretation of the eight source bits.

P2R is a VEC Tile operation. Each participating PE reads the eight selectors from its own architectural scalar-GPR file and publishes its own Local CellReg result. It follows the ordinary Tile PE_MASK contract; PE_MASK=0000 is a strict no-op before GPR reads, offset validation, descriptor checks, allocation, or payload effects. Complete operand-count, offset, type, layout, capacity, and allocation preflight precedes all source snapshots. Malformed operands, a non-U8/non-M32 destination, an offset outside 0..3, insufficient destination capacity, or allocation failure raises the ordinary Tile legality/allocation fault before effects.

An implementation may split P2R into four chained uops over (P0/P1, P2/P3, P4/P5, P6/P7) or use another internal grouping. Each internal uop may start when its own two GPR values and incoming partial result are ready; it need not wait for all eight GPRs. Uop count, grouping, scheduling, and latency are not architectural, and no internal partial result is architecturally observable.

Two motivating lowerings require this exact bit transpose:

1. HiF4X2 data packing. Assign P0..P3 to the four output bitplanes of the low FP16 element and P4..P7 to the high FP16 element. At the selected byte offset, D[r,byte_offset][3:0] is the low HiF4 encoding and D[r,byte_offset][7:4] is the high HiF4 encoding, matching the accepted low-nibble-first packed-X2 rule. One 32-row result carries 64 logical HiF4 values.
2. HiF4 scale-field packing. Across 32 rows/groups, one P2R forms the eight E1_8 bits and two P2Rs form the low and high bytes of the sixteen E1_16 bits. These bytes combine with E6M2 under the accepted raw-U32 layout:

bits[7:0]   = E6M2
bits[15:8]  = P2R(E1_8[0..7])
bits[23:16] = P2R(E1_16[0..7])
bits[31:24] = P2R(E1_16[8..15])

The public motivation is Algorithm 1 of HiFloat4 Format for Language Model Inference, where E1_8 and E1_16 are produced by compare decisions. The paper motivates the use case but does not own PTO instruction semantics.

Required contract replacements and representability work

• TCMP/TSEL currently bind a packed predicate Tile through B.IOT. APPLY must replace that operand/result surface with ordered architectural GPR operands and update ADR-0080 plus every dependent contract and test.
• B.IOR binds at most three GPR sources, one GPR destination, and may appear at most once per block. It cannot represent TCMP's variable GPR result count, TSEL's predicate GPR inputs, or P2R's eight GPR inputs without a new or extended encoding carrier.
• A U8 CUBE_M32 offset-column result defines one selected byte in each 32-bit lane and leaves the other bytes Null. Descriptor/subview support must represent that selected column explicitly; it must not reinterpret undefined bytes or silently change the destination type.
• Producing three U8 scale fields does not by itself define the final lane-local U8-to-raw-U32 assembly operation; that is a separate instruction/dataflow decision and does not change P2R's eight-GPR transpose.

These are architecture decisions, not executor-discretion items.

Defaults and intentionally unspecified behavior

• P2R has no implicit merge seed and never reads an old destination. A new destination is allocated and published atomically.
• No omitted operand silently supplies a predicate plane. Encoded GPR zero supplies an all-zero plane and remains distinct from omission.
• Omitted P2R byte offset selects byte zero. Explicit offsets zero through three select the corresponding U8 column; no modulo or truncation is applied to an illegal value.
• Physical-register assignment, RAT organization, issue-queue topology, payload collection, uop count, uop grouping, bypass, latency, and throughput are intentionally unspecified.
• The architectural predicate carrier is an ordinary GPR. An implementation may reuse its physical GPR storage, rename, wakeup, and writeback structures; that reuse does not make any particular physical register number architectural.
• No relationship to NVIDIA register names, encodings, or completion behavior is architectural.

Compatibility and toolchain impact

This decision makes predicate GPRs architecturally visible and changes TCMP/TSEL from predicate-Tile operands to GPR operands. It is therefore a hard compatibility change to ADR-0080, PTO-TCMP-CONTRACT-001, PTO-TSEL-CONTRACT-001, their current block schemas, and existing binaries that encode those schemas. APPLY must not present this as a physical-storage-only implementation detail.

The new P2R mnemonic and the replacement TCMP/TSEL operand carrier move reserved encoding space to assigned and require assembler, disassembler, compiler, intrinsic, executable model, RTL, catalog, decoder-witness, and dependent-tool updates.

No encoding is proposed in this issue. APPLY must perform an exact-head collision audit after the operand surface is frozen.

Encoding work intentionally left open

The only architecture surface intentionally not proposed here is the bit encoding and its concrete bundle carrier: selectors/opcode allocation, how TCMP's ordered GPR destination list, TSEL's ordered GPR source list, P2R's eight GPR sources and U8 byte offset are encoded, and the corresponding canonical assembly spelling. The selected encoding may reuse the existing PadValueOrByteId/ByteId0..3 field for the offset, but is not required to do so. It must preserve the operand order and behavior defined above without weakening existing surplus-field, omission-versus-zero, preflight, or fault rules.

ASL changes are blocked until that encoding is resolved by an accepted architecture decision.

Verification evidence required by APPLY

• TCMP M32 FP16x2 evidence proving exactly two GPR results, P0[r] from the low half and P1[r] from the high half, for lane 0/31 and mixed lane patterns.
• TSEL FP16x2 evidence proving those same two ordered GPR inputs independently control the low and high halves of each lane.
• Multi-Cell M32 and M16 evidence proving GPR order is logical Cell first and within-Cell slot second; M16 proves only bits 15:0 name rows and bits 31:16 follow predicate padding definedness.
• A capacity-boundary test proving an oversized TCMP GPR destination list rejects atomically and can be reproduced by software-split smaller Tiles.
• Scalar producer/consumer evidence proving TCMP results are readable by scalar instructions and scalar-written GPRs are legal TSEL/P2R inputs.
• One decoded legal P2R operation proving D[r,byte_offset][b] = Pb[r] for all eight architectural GPR sources and each offset 0..3.
• Walking-one coverage across plane 0/7 and row 0/31, plus repeated/all-zero/all-one sources.
• HiF4X2 packing with low nibble 0x5, high nibble 0xA, and exact output byte 0xA5.
• Walking-one coverage of the three HiF4 scale-field placements and one complete E6M2/E1_8/E1_16 word assembled by explicit downstream operations.
• Minimum/maximum valid-row and tail cases for TCMP/TSEL, including Null and explicit predicate padding values.
• Malformed/missing/surplus operands, repeated or non-writable TCMP destinations, illegal P2R offset, wrong destination type/layout/shape, insufficient capacity, and allocation failure, all before effects.
• Repeated/all-zero/all-one TSEL and P2R GPR sources; TSEL data-source/destination aliases retain read-old snapshot behavior.
• PE-mask-zero no-effect behavior under the ordinary Tile mask contract.
• Regression evidence that TCMP comparison results, TSEL exact selection, HiF4 scale decoding, and unrelated binaries remain unchanged apart from the deliberately replaced TCMP/TSEL operand schemas.
• Generated instruction page, catalog, decoder witness, NDF traceability, AVS inventory, and projection-drift checks.

Explicit exclusions

• mandating physical GPR numbers, GPR RAT, CellReg RAT, separate issue queues, payload-fill wakeup, four uops, or any cycle latency;
• changing TCMP comparison relations, supported numeric types, NaN/status behavior, or TSEL's exact selection behavior beyond replacing the predicate-Tile carrier with the ordered GPR-plane mapping above;
• changing the accepted HiF4 raw-U32 scale format or Matrix scale CellReg order;
• defining the complete BF16-to-HiF4 numeric conversion, rounding, threshold generation, or fused multiply-convert operations;
• downstream compiler/RTL adoption, release version assignment, tagging, or publication.

Release impact

Required - normative or release-evidence change.

The issue/design record is not implementation or release evidence. Any later APPLY requires fresh exact-head manual release verification for the accepted architecture and generated evidence.

[ckwllawliet]

Frozen design contract for #152, coordinated with #160. This records the architecture decision only; it does not close the issue.

The additive CUBE extension applies to TCMP/TCMPS/TSEL/TSELS and supports only CUBE_M16 and CUBE_M32. Each operation selects exactly one predicate carrier: either GPR or CellReg. Mixed carriers and implicit conversions are illegal.

GPRs remain 64-bit with the existing 24-register architectural namespace, and B.IOR remains the GPR binder. A GPR-producing TCMP/TCMPS has at most one destination GPR.

For GPR-producing compares:

• CUBE_M32/U32 accepts one CellReg for a low-32-bit result or two spatial CellRegs for one complete 64-bit result.
• CUBE_M32/U16 and BF16 place the two predicate columns in GPR[31:0] and GPR[63:32].
• CUBE_M32/U8 selects columns 0..1 or 2..3 through the operation-specific SatMode interpretation of B.DATR.Sat.
• CUBE_M16/U32 uses the low 32 bits, with the two predicate columns in bits [15:0] and [31:16].
• CUBE_M16/U16 and BF16 pack four 16-bit predicate fields into the four 16-bit fields of the GPR.
• CUBE_M16/U8 selects columns 0..3 or 4..7 through the same explicit SatMode convention.

TSEL/TSELS support both complete carrier schemas. A GPR predicate mask is bound through the predicate-specific B.IOR source role; a CellReg predicate mask is the first B.IOT PredicateCell source. The schemas are mutually exclusive and are not inferred from payload values. TSEL/TSELS use the target-shape-complete mask: U32 can consume one complete GPR for up to two 32-bit regions, while U8 consumes two complete GPRs.

The related conversion is named TGPR2T. It is a layout re-encoding, not bit-to-byte widening. It consumes four ordered source-only GPRs through two contiguous B.IOR records, produces an ordinary CUBE U8 Tile, and uses Mode 3 Function 30 (0x07E). PadValue remains in B.DATR.PadValueOrByteId; ByteOffset uses RMode[16:15], with RMode[17] reserved-zero.

Forwarding is implementation-only and is not part of the ISA contract. The implementation PR should update the authoritative ASL/NDF owners, generated projections, decoder/catalog closure, and focused evidence for the accepted and rejected carrier schemas.