comp_pc.dv

set link_library "./vhdl/mips_pipeline/mem/SPHDL100823_nom_1.20V_25C.db $link_library"
set target_library "./vhdl/mips_pipeline/mem/SPHDL100823_nom_1.20V_25C.db $target_library"


analyze -library work -format vhdl ./vhdl/mips_pipeline/subtypes_pkg.vhd
analyze -library work -format vhdl ./vhdl/mips_pipeline/records_pkg.vhd
analyze -library work -format vhdl ./vhdl/mips_pipeline/constants_pkg.vhd
analyze -library work -format vhdl ./vhdl/mips_pipeline/components_pkg.vhd

analyze -library work -format vhdl ./vhdl/mips_pipeline/if/pc.vhd
analyze -library work -format vhdl ./vhdl/mips_pipeline/if/if_top.vhd

elaborate if_top -architecture Behavioral -library work

# Make sure the compiler does not exchange pads.
#set_dont_touch [ get_cells *pad*] true
#set_dont_touch clk_pad_in true

# test test
#set_dont_touch alu_result* true

# Fix the clock (ns).
create_clock -period 15 -name myclk clk
set_clock_uncertainty 1 myclk

# Do the real synthesis.
#set_max_area 0
compile -map_effort high -area_effort high

# Save the stuff

report_area
report_timing