From 243f91a59c5345263b398fb8e80dd713cf823b27 Mon Sep 17 00:00:00 2001 From: Eric Wang Date: Tue, 28 Jul 2026 13:39:30 -0700 Subject: [PATCH] shims: let the transceiver boot before clocking SPI mmhal_wlan_hard_reset() waited 20ms after releasing RESET_N. That covers the reset pulse but not the transceiver's boot, and the SD over SPI startup handshake begins clocking as soon as it returns: a training sequence, then a poll for the command response, well over a thousand clock edges. A transceiver that is still booting can latch onto a bit phase that is not byte aligned with the host's framing and hold it for the rest of the boot. The symptom is misleading. Every SPI transfer succeeds and the response itself is intact, just offset by a few bit periods, so the driver rejects it as an invalid ack and the failure presents as absent or faulty hardware. It is intermittent, and more likely on boards where concurrent activity delays the handshake relative to the reset. Wait CONFIG_MM_RESET_SETTLE_MS before the first clock edge instead. This is Kconfig rather than a constant because the delay a board needs depends on its transceiver and firmware image, so a board with a known-shorter boot can tune it down. The 20ms default is unchanged for backwards compatibility, but systems that need a longer duration can now override this. For example, on an ESP32-C5 with an MM8108, boots failed at 20ms and were clean from 30ms upward; a reset settle delay of 100ms would provide a safe margin to ensure successful transceiver boot. Signed-off-by: Eric Wang --- halow/components/shims/Kconfig | 18 ++++++++++++++++++ halow/components/shims/mmhal_wlan.c | 2 +- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/halow/components/shims/Kconfig b/halow/components/shims/Kconfig index 5c3a950..a680dc8 100644 --- a/halow/components/shims/Kconfig +++ b/halow/components/shims/Kconfig @@ -7,6 +7,24 @@ menu "Morse Micro Shim Configuration" help Output gpio pin used to control the RESET_N line. + config MM_RESET_SETTLE_MS + int "Delay after releasing RESET_N, in milliseconds" + default 20 + range 1 1000 + help + Delay between releasing RESET_N and the first SPI clocking. This must cover the + transceiver's boot, not just its reset pulse. + + The startup handshake clocks a training sequence and then polls for the command + response. A transceiver that is still booting when that clocking starts can latch + onto a bit phase that is not byte aligned with the host's framing and hold it for + the rest of the boot, so the handshake reads a correct response at the wrong + alignment and the driver rejects it as an invalid ack. The failure is intermittent + and looks like absent or faulty hardware. + + Adjust this based on the boot time measured on your particular board to ensure + that the transceiver has sufficient time to boot. + config MM_WAKE int "WAKE pin for MM chip" default -1 diff --git a/halow/components/shims/mmhal_wlan.c b/halow/components/shims/mmhal_wlan.c index a25783c..4a58b15 100644 --- a/halow/components/shims/mmhal_wlan.c +++ b/halow/components/shims/mmhal_wlan.c @@ -176,7 +176,7 @@ void mmhal_wlan_hard_reset(void) gpio_set_level(CONFIG_MM_RESET_N, 0); mmosal_task_sleep(5); gpio_set_level(CONFIG_MM_RESET_N, 1); - mmosal_task_sleep(20); + mmosal_task_sleep(CONFIG_MM_RESET_SETTLE_MS); } void mmhal_wlan_spi_cs_assert(void)