Reset behaviour

[Jpnock]

We should standardise reset behaviour across the different units.

For example, register file will reset as long as reset is high during the posedge of the clock whereas PC only resets if reset was high combinationally, in cycle N, but gets lowered during cycle N+1

[Jpnock]

#16 (comment)

This will also need to be looked at after merging

[JoachimSand]

"All signals are synchronous to clk, including reset. The reset signal must be held high for at least 1 cycle to reset the CPU. This is a level-sensitive reset, which is synchronous to the clock."

I think the standard reset functionality should be the one the PC currently follows.

[Jpnock]

Linking this as it seems relevant

The general pattern for updating registers with a clock enable is:

always_ff @(posedge clk) begin
    if (reset) then begin
        /* Do reset logic */
        my_ff <= ... ;
    end
    else if(clk_enable) then
        /* Perform clock update */
        m_ff <= ... ;
    end
end