Makefile

# ==============================================================================
# Duck Server — Cocotb Simulation Makefile
# Simulator: Icarus Verilog (SIM=icarus) or VCS (SIM=vcs)
# ==============================================================================

SIM          ?= icarus
TOPLEVEL_LANG ?= verilog

VERILOG_SOURCES  = $(PWD)/rtl/alu.sv
VERILOG_SOURCES += $(PWD)/rtl/imm_decode.sv
VERILOG_SOURCES += $(PWD)/rtl/register_file.sv
VERILOG_SOURCES += $(PWD)/rtl/riscv_core.sv
VERILOG_SOURCES += $(PWD)/rtl/noc_router.sv
VERILOG_SOURCES += $(PWD)/rtl/l2_cache.sv
VERILOG_SOURCES += $(PWD)/rtl/duck_coherency_ctrl.sv
VERILOG_SOURCES += $(PWD)/rtl/pe.sv
VERILOG_SOURCES += $(PWD)/rtl/npu.sv
VERILOG_SOURCES += $(PWD)/rtl/gpu.sv
VERILOG_SOURCES += $(PWD)/rtl/ucie_chan.sv
VERILOG_SOURCES += $(PWD)/rtl/ucie_link_ctrl.sv
VERILOG_SOURCES += $(PWD)/rtl/cpu_chiplet_top.sv
VERILOG_SOURCES += $(PWD)/rtl/npu_chiplet_top.sv
VERILOG_SOURCES += $(PWD)/rtl/base_die_top.sv
VERILOG_SOURCES += $(PWD)/rtl/system_top.sv

TOPLEVEL = system_top

# Override on the command line to run a different testbench, e.g.:
#   make MODULE=tb_moesi_integration ASM_TEST=moesi_weight_test.asm
# or via Docker:
#   docker run -e MODULE=tb_moesi_integration -e ASM_TEST=moesi_weight_test.asm ...
MODULE  ?= tb_server_dispatch_unit

# Python test module (no .py extension) — follows MODULE
COCOTB_TEST_MODULES = $(MODULE)

# Let cocotb find our testbench Python module
export PYTHONPATH := $(PWD)/tb:$(PYTHONPATH)

# Expose ASM_TEST so it can be overridden on the command line:
#   make ASM_TEST=my_custom.asm
export ASM_TEST ?= cpu_peak_tests.asm

# Icarus: enable SystemVerilog and suppress common style warnings
COMPILE_ARGS += -g2012

include $(shell cocotb-config --makefiles)/Makefile.sim