soc_scripts/gen_tb.py at master · EdenSunYuan/soc_scripts · GitHub

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#!/home/tladmin/EDA_tools/mentor/calibre/aoi_cal_2018.4_34.26/bin/python3

import re
import os
import sys

print('-----TB Generator-----')
#open the design file
#file_design = input('Please enter the file name:')
file_design=''
try:
  file_design = sys.argv[1]
except Exception:
  raise ("gen_tb.py need a parameter, example: ./gen_tb.py design.v ")
file_tb     = 'tb_top.v'

directory = os.getcwd()
file_path = directory+'/'+file_design
print('Current path: '+directory)

with open(file_path,'r') as file_obj:
  print('Read instance: '+file_path)
  content = file_obj.read()
  #delete verilog comment
  regex_note=re.compile(r'//.*')
  match_string=re.findall(regex_note, content)
  for k in range(len(match_string)):
    content=content.replace(match_string[k],'')

  #regex match module name
  regex_module = re.compile(r'(module)(\s+)(\w+)(\s+)')
  module_obj = re.findall(regex_module, content);
  if len(module_obj)==0:
    print('Error! Cannot find any module')
  if len(module_obj)>1:
    print('Error! ',len(module_obj), ' module have been found')
  if len(module_obj)==1:
    print('Find module: ',module_obj[0][2])

  #regex match ports name
  regex_ports = re.compile(r'(input|output)(\s+)(reg|wire)?(\s+)?(\[.*:.*\]\s+)?(\w+)');
  groups_ports = re.findall(regex_ports, content)
  print('Find ports:',len(groups_ports))

  ##write the instantiation templete to an assigned file
  with open(directory+'/'+file_tb,'w') as file_obj2:
    #
    file_obj2.write('''//This file is generated by scripts for simulation
    \n//The simulation is for smoking test
    \n//hengfeng.zhang
    \n`timescale 1ns/1ps
    \nmodule tb_top;
    ''')
    #generated dut
    if module_obj is not None:
      num = len(groups_ports)
      #generated signals declaration
      file_obj2.write('\n//Declaration DUT signals')
      for i in range(num):
        if groups_ports[i][0] == 'input':
          file_obj2.write('\nreg  \t'+groups_ports[i][4]+'\t'+groups_ports[i][5]+';')
        else:
          file_obj2.write('\nwire \t'+groups_ports[i][4]+'\t'+groups_ports[i][5]+';')
      #generated instance
      file_obj2.write('\n\n//Instance DUT module')
      file_obj2.write('\n'+module_obj[0][2]+' u_'+module_obj[0][2]+' (\n')
      for i in range(num):
        if i == num-1:
          file_obj2.write('\t.'+groups_ports[i][5]+'\t('+groups_ports[i][5]+')'+'\t //'+groups_ports[i][0]+groups_ports[i][4]+'\n);\n')
        else:
          file_obj2.write('\t.'+groups_ports[i][5]+'\t('+groups_ports[i][5]+'),'+'\t //'+groups_ports[i][0]+groups_ports[i][4]+'\n')

    #load template for simulation
    with open(directory+'/'+'simulation.temp','r') as file_temp:
      file_obj2.write(file_temp.read())

    #generated endmodule
    file_obj2.write('\n\nendmodule')

  print('----Generator Report-----\ntb_top.v have been generated!!!')
  #regex match parameter define
  regex_para = re.compile(r'parameter')
  groups_para = re.findall(regex_para, content)
  if len(groups_para) > 0:
    print('Attention!!! Find module parameters', len(groups_para))
    print('Please Check if your instance use default parameter!!!')