From f3e2146aa185f1db1657ec7a16327106cd938f28 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Cl=C3=A9ment=20Chaine?= <clement.chaine25@gmail.com>
Date: Sun, 23 Nov 2025 10:27:19 +0100
Subject: [PATCH 01/15] Integrate testlib v1.1.0

---
 CMakeLists.txt             |   4 +-
 config/verible-lint.rules  |   4 --
 config/verible-lint.waives |   2 -
 tests/CMakeLists.txt       | 107 +++++++++++++++----------------------
 4 files changed, 46 insertions(+), 71 deletions(-)
 delete mode 100644 config/verible-lint.rules
 delete mode 100644 config/verible-lint.waives

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 5805518..5d33cc9 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -51,7 +51,7 @@ add_dependency(ECAP5_TREQ
 
 add_dependency(ECAP5_DTESTLIB
   GIT ecap5/ecap5-dtestlib
-  TAG tags/v1.0.0)
+  TAG 29-add-add_testbench-cmake-function-to-this-repository)
 
 add_dependency(sphinx-cmake
   GIT ecap5/sphinx-cmake
@@ -71,6 +71,8 @@ include(${verilator_cmake_SOURCE_DIR}/cmake/verilator-config.cmake)
 include(${ecap5_treq_SOURCE_DIR}/config.cmake)
 list(APPEND CMAKE_MODULE_PATH "${sphinx_cmake_SOURCE_DIR}/cmake")
 include(${oss_cad_suite_cmake_SOURCE_DIR}/cmake/oss-cad-suite-config.cmake)
+include(${ecap5_dtestlib_SOURCE_DIR}/cmake/testbench.cmake)
+include(${ecap5_dtestlib_SOURCE_DIR}/cmake/lint.cmake)
 
 # Include subdirectories
 
diff --git a/config/verible-lint.rules b/config/verible-lint.rules
deleted file mode 100644
index d379925..0000000
--- a/config/verible-lint.rules
+++ /dev/null
@@ -1,4 +0,0 @@
--no-trailing-spaces
--line-length
--explicit-parameter-storage-type
-+parameter-name-style="localparam_style:ALL_CAPS"
diff --git a/config/verible-lint.waives b/config/verible-lint.waives
deleted file mode 100644
index 139597f..0000000
--- a/config/verible-lint.waives
+++ /dev/null
@@ -1,2 +0,0 @@
-
-
diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt
index 1220eca..5ffac30 100644
--- a/tests/CMakeLists.txt
+++ b/tests/CMakeLists.txt
@@ -4,92 +4,71 @@
 # \__/\__/_//_/\_,_/_/_//_/\__/
 # 
 # Copyright (C) Clément Chain
-# This file is part of ECAP5-DPROC <https://github.com/cchaine/ECAP5-DPROC>
+# This file is part of ECAP5-DWBUART <https://github.com/ecap5/ECAP5-DWBUART>
 # 
-# ECAP5-DPROC is free software: you can redistribute it and/or modify
+# ECAP5-DWBUART is free software: you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
 # the Free Software Foundation, either version 3 of the License, or
 # (at your option) any later version.
 # 
-# ECAP5-DPROC is distributed in the hope that it will be useful,
+# ECAP5-DWBUART is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 # 
 # You should have received a copy of the GNU General Public License
-# along with ECAP5-DPROC.  If not, see <http://www.gnu.org/licenses/>.
+# along with ECAP5-DWBUART.  If not, see <http://www.gnu.org/licenses/>.
 
+# Bench parent directory
 set(BENCH_DIR ${CMAKE_CURRENT_SOURCE_DIR}/benches/)
+# C++ bench include directory
 set(TEST_INCLUDE_DIR ${ecap5_dtestlib_SOURCE_DIR}/include)
-set(SRC_DIR ${CMAKE_SOURCE_DIR}/src/)
+# HDL source directories
+set(SRC_DIRS ${CMAKE_SOURCE_DIR}/src/)
+# HDL library directories
 set(LIBS_DIR ${ecap5_dtestlib_SOURCE_DIR}/src/)
+# Bench CSV output directory
 set(TESTDATA_DIR ${CMAKE_CURRENT_BINARY_DIR}/testdata/)
-set(CONFIG_DIR ${CMAKE_SOURCE_DIR}/config/)
-
-# Create folders for the waves and testdata
-file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/waves)
-file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/testdata)
 
 # Lint
-file(GLOB SRC_FILES ${SRC_DIR}/*.sv)
-add_custom_target(lint 
-  COMMAND verible-verilog-lint ${SRC_FILES} --rules_config="${CONFIG_DIR}/verible-lint.rules" --waiver_files="${CONFIG_DIR}/verible-lint.waives"
-  DEPENDS ${SRC_FILES})
-
-# Testbench
-set(TEST_BINARIES)
-set(TEST_TARGETS)
-set(TEST_OUTPUTS)
-macro(add_testbench module)
-  cmake_parse_arguments(ARG ""
-                            "BENCH"
-                            "LIBS"
-                            ${ARGN})
+add_lint_target(
+  TARGET lint
+  SRC_DIRS ${SRC_DIRS}
+)
 
-  if("${ARG_BENCH}" STREQUAL "")
-    set(ARG_BENCH ${module})
-  endif()
-  set(TARGET tb_${ARG_BENCH})
+# Add testbenches
+add_testbench(
+  MODULE       rx_frontend
+  BENCH_DIR    ${BENCH_DIR}
+  LIBS_DIR     ${LIBS_DIR}
+  TESTDATA_DIR ${TESTDATA_DIR}
+  SRC_DIRS     ${SRC_DIRS} 
+)
 
-  # Make a file list for testing libraries
-  list(TRANSFORM ARG_LIBS APPEND ".sv")
-  list(TRANSFORM ARG_LIBS PREPEND ${LIBS_DIR})
+add_testbench(
+  MODULE       tx_frontend
+  BENCH_DIR    ${BENCH_DIR}
+  LIBS_DIR     ${LIBS_DIR}
+  TESTDATA_DIR ${TESTDATA_DIR}
+  SRC_DIRS     ${SRC_DIRS} 
+)
 
-  # Create the test executable
-  add_executable(${TARGET} ${BENCH_DIR}/${module}/${TARGET}.cpp)
-  target_include_directories(${TARGET} PUBLIC ${TEST_INCLUDE_DIR})
-  verilate(${TARGET}
-    PREFIX V${TARGET}
-    SOURCES ${BENCH_DIR}/${module}/${TARGET}.sv
-            ${ARG_LIBS}
-    INCLUDE_DIRS ${SRC_DIR}
-    TRACE)
+add_testbench(
+  MODULE       wb_interface
+  BENCH_DIR    ${BENCH_DIR}
+  LIBS_DIR     ${LIBS_DIR}
+  TESTDATA_DIR ${TESTDATA_DIR}
+  SRC_DIRS     ${SRC_DIRS} 
+)
 
-  set(TEST_TARGET simulate_${ARG_BENCH})
-  set(TEST_OUTPUT ${TESTDATA_DIR}/${ARG_BENCH}.csv)
-  # Create the ${TEST_TARGET} command to run the test
-  get_target_property(BINARY_DIR "${TARGET}" BINARY_DIR)
-  if(${DEBUGLOG})
-    set(RUN_TARGET_ARGUMENT "-v")  
-  endif()
-  add_custom_command(
-    COMMAND ${TARGET} ${RUN_TARGET_ARGUMENT}
-    OUTPUT ${TEST_OUTPUT}
-    DEPENDS ${TARGET}
-    WORKING_DIRECTORY ${CMAKE_PROJECT_DIR})
-  add_custom_target(${TEST_TARGET} DEPENDS ${TEST_OUTPUT})
-  # Add the ${TEST_TARGET} target to the test targets
-  list(APPEND TEST_BINARIES ${TARGET})
-  list(APPEND TEST_TARGETS ${TEST_TARGET})
-  list(APPEND TEST_OUTPUTS ${TEST_OUTPUT})
-endmacro()
-
-add_testbench(rx_frontend)
-add_testbench(tx_frontend)
-add_testbench(wb_interface)
-add_testbench(ecap5_dwbuart)
+add_testbench(
+  MODULE       ecap5_dwbuart
+  BENCH_DIR    ${BENCH_DIR}
+  LIBS_DIR     ${LIBS_DIR}
+  TESTDATA_DIR ${TESTDATA_DIR}
+  SRC_DIRS     ${SRC_DIRS} 
+)
 
 # Main targets
 add_custom_target(build DEPENDS ${TEST_BINARIES})
 add_custom_target(tests DEPENDS ${TEST_TARGETS})
-

From 42beca599ed2354beb2e2ccbee399137cc0f33b4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Cl=C3=A9ment=20Chaine?= <clement.chaine25@gmail.com>
Date: Tue, 25 Nov 2025 17:45:07 +0100
Subject: [PATCH 02/15] Use ecap5_dwbmmsc

---
 CMakeLists.txt                                |   8 +-
 src/ecap5_dwbuart.sv                          |   7 +-
 src/wb_interface.sv                           | 105 ------
 tests/CMakeLists.txt                          |  10 +-
 .../benches/wb_interface/tb_wb_interface.cpp  | 341 ------------------
 tests/benches/wb_interface/tb_wb_interface.sv |  74 ----
 6 files changed, 11 insertions(+), 534 deletions(-)
 delete mode 100644 src/wb_interface.sv
 delete mode 100644 tests/benches/wb_interface/tb_wb_interface.cpp
 delete mode 100644 tests/benches/wb_interface/tb_wb_interface.sv

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 5d33cc9..747e8ef 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -51,7 +51,11 @@ add_dependency(ECAP5_TREQ
 
 add_dependency(ECAP5_DTESTLIB
   GIT ecap5/ecap5-dtestlib
-  TAG 29-add-add_testbench-cmake-function-to-this-repository)
+  TAG release/v1.1.0)
+
+add_dependency(ECAP5_DWBMMSC
+  GIT ecap5/ecap5-dwbmmsc
+  TAG release/v1.0.0)
 
 add_dependency(sphinx-cmake
   GIT ecap5/sphinx-cmake
@@ -82,7 +86,7 @@ add_subdirectory(tests)
 # Synthesis
 
 add_synthesis_target(
-  SOURCES ${CMAKE_CURRENT_LIST_DIR}/src/*
+  SOURCES ${CMAKE_CURRENT_LIST_DIR}/src/* ${ecap5_dwbmmsc_SOURCE_DIR}/src/*
   TOP_MODULE ecap5_dwbuart
   TARGET_FPGA ecp5
   OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/synth.json)
diff --git a/src/ecap5_dwbuart.sv b/src/ecap5_dwbuart.sv
index 89e683f..e2c4f90 100644
--- a/src/ecap5_dwbuart.sv
+++ b/src/ecap5_dwbuart.sv
@@ -66,7 +66,7 @@ module ecap5_dwbuart #(
 
 logic frontend_rst;
 
-logic[7:0]  mem_addr;
+logic[31:0] mem_addr;
 logic       mem_read, mem_write;
 logic[31:0] mem_read_data_d, mem_read_data_q, 
             mem_write_data;
@@ -137,7 +137,7 @@ tx_frontend #(
   .uart_tx_o      (uart_tx_o)
 );
 
-wb_interface wb_interface_inst (
+ecap5_dwbmmsc wb_interface_inst (
   .clk_i (clk_i),   .rst_i (rst_i),
   
   .wb_adr_i (wb_adr_i),  .wb_dat_o (wb_dat_o),  .wb_dat_i   (wb_dat_i),
@@ -148,7 +148,8 @@ wb_interface wb_interface_inst (
   .read_o       (mem_read),
   .read_data_i  (mem_read_data_q),
   .write_o      (mem_write),
-  .write_data_o (mem_write_data)
+  .write_data_o (mem_write_data),
+  .sel_o          ()
 );
 
 always_comb begin : register_access
diff --git a/src/wb_interface.sv b/src/wb_interface.sv
deleted file mode 100644
index 151ad80..0000000
--- a/src/wb_interface.sv
+++ /dev/null
@@ -1,105 +0,0 @@
-/*           __        _
- *  ________/ /  ___ _(_)__  ___
- * / __/ __/ _ \/ _ `/ / _ \/ -_)
- * \__/\__/_//_/\_,_/_/_//_/\__/
- * 
- * Copyright (C) Clément Chaine
- * This file is part of ECAP5-DWBUART <https://github.com/ecap5/ECAP5-DWBUART>
- *
- * ECAP5-DWBUART is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * ECAP5-DWBUART is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with ECAP5-DWBUART.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-module wb_interface
-(
-  input   logic         clk_i,
-  input   logic         rst_i,
-
-  //=================================
-  //    Memory interface
-
-  input   logic[31:0]  wb_adr_i,
-  output  logic[31:0]  wb_dat_o,
-  input   logic[31:0]  wb_dat_i,
-  input   logic        wb_we_i,
-  input   logic[3:0]   wb_sel_i,
-  input   logic        wb_stb_i,
-  output  logic        wb_ack_o,
-  input   logic        wb_cyc_i,
-  output  logic        wb_stall_o,
-
-  //=================================
-  //    Output interface
-
-  output  logic[7:0]   addr_o,
-  output  logic        read_o,
-  input   logic[31:0]  read_data_i,
-  output  logic        write_o,
-  output  logic[31:0]  write_data_o
-);
-/*****************************************/
-/*           Internal signals            */
-/*****************************************/
-
-typedef enum logic[1:0] {
-  IDLE,
-  RESPONSE
-} state_t;
-state_t state_d, state_q;
-
-/*****************************************/
-/*            Output signals             */
-/*****************************************/
-
-logic wb_ack_d, wb_ack_q;
-
-/*****************************************/
-
-always_comb begin : wishbone
-  state_d = state_q;
-  wb_ack_d = 0;
-
-  case(state_q)
-    IDLE: begin
-      if(wb_stb_i && wb_cyc_i) begin
-        wb_ack_d = 1;
-        state_d = RESPONSE;
-      end
-    end
-    RESPONSE: begin
-      state_d = IDLE;
-    end
-    default: begin end
-  endcase
-end
-
-always_ff @(posedge clk_i) begin
-  if(rst_i) begin
-    state_q <= IDLE;
-    wb_ack_q <= 0;
-  end else begin
-    state_q  <=  state_d;
-    wb_ack_q <= wb_ack_d;
-  end
-end
-
-assign wb_ack_o = wb_ack_q;
-assign wb_dat_o = read_data_i;
-assign wb_stall_o = 0;
-
-assign addr_o = wb_adr_i[7:0];
-assign read_o  = wb_stb_i && wb_cyc_i && ~wb_we_i;
-assign write_o = wb_stb_i && wb_cyc_i && wb_we_i;
-assign write_data_o = wb_dat_i;
-
-endmodule // wb_interface
diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt
index 5ffac30..2f63a84 100644
--- a/tests/CMakeLists.txt
+++ b/tests/CMakeLists.txt
@@ -24,7 +24,7 @@ set(BENCH_DIR ${CMAKE_CURRENT_SOURCE_DIR}/benches/)
 # C++ bench include directory
 set(TEST_INCLUDE_DIR ${ecap5_dtestlib_SOURCE_DIR}/include)
 # HDL source directories
-set(SRC_DIRS ${CMAKE_SOURCE_DIR}/src/)
+set(SRC_DIRS ${CMAKE_SOURCE_DIR}/src/ ${ecap5_dwbmmsc_SOURCE_DIR}/src/)
 # HDL library directories
 set(LIBS_DIR ${ecap5_dtestlib_SOURCE_DIR}/src/)
 # Bench CSV output directory
@@ -53,14 +53,6 @@ add_testbench(
   SRC_DIRS     ${SRC_DIRS} 
 )
 
-add_testbench(
-  MODULE       wb_interface
-  BENCH_DIR    ${BENCH_DIR}
-  LIBS_DIR     ${LIBS_DIR}
-  TESTDATA_DIR ${TESTDATA_DIR}
-  SRC_DIRS     ${SRC_DIRS} 
-)
-
 add_testbench(
   MODULE       ecap5_dwbuart
   BENCH_DIR    ${BENCH_DIR}
diff --git a/tests/benches/wb_interface/tb_wb_interface.cpp b/tests/benches/wb_interface/tb_wb_interface.cpp
deleted file mode 100644
index 4e2641d..0000000
--- a/tests/benches/wb_interface/tb_wb_interface.cpp
+++ /dev/null
@@ -1,341 +0,0 @@
-/*           __        _
- *  ________/ /  ___ _(_)__  ___
- * / __/ __/ _ \/ _ `/ / _ \/ -_)
- * \__/\__/_//_/\_,_/_/_//_/\__/
- * 
- * Copyright (C) Clément Chaine
- * This file is part of ECAP5-DWBUART <https://github.com/ecap5/ECAP5-DWBUART>
- *
- * ECAP5-DWBUART is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * ECAP5-DWBUART is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with ECAP5-DWBUART.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <time.h>
-#include <verilated.h>
-#include <verilated_vcd_c.h>
-#include <svdpi.h>
-
-#include "Vtb_wb_interface.h"
-#include "testbench.h"
-
-enum CondId {
-  COND_output = 0,
-  COND_wishbone,
-  __CondIdEnd
-};
-
-enum TestcaseId {
-  T_RESET = 1,
-  T_READ,
-  T_WRITE
-};
-
-class TB_Wb_interface : public Testbench<Vtb_wb_interface> {
-public:
-  void reset() {
-    this->_nop();
-
-    this->core->rst_i = 1;
-    for(int i = 0; i < 5; i++) {
-      this->tick();
-    }
-    this->core->rst_i = 0;
-
-    Testbench<Vtb_wb_interface>::reset();
-  }
-  
-  void _nop() {
-    this->core->wb_adr_i = 0;
-    this->core->wb_dat_i = 0;
-    this->core->wb_we_i = 0;
-    this->core->wb_sel_i = 0;
-    this->core->wb_stb_i = 0;
-    this->core->wb_cyc_i = 0;
-  }
-
-  void read(uint32_t addr) {
-    this->core->wb_adr_i = addr;
-    this->core->wb_dat_i = 0;
-    this->core->wb_we_i = 0;
-    this->core->wb_sel_i = 0xF;
-    this->core->wb_stb_i = 1;
-    this->core->wb_cyc_i = 1;
-  }
-
-  void write(uint32_t addr, uint32_t data) {
-    this->core->wb_adr_i = addr;
-    this->core->wb_dat_i = data;
-    this->core->wb_we_i = 1;
-    this->core->wb_sel_i = 0xF;
-    this->core->wb_stb_i = 1;
-    this->core->wb_cyc_i = 1;
-  }
-};
-
-void tb_wb_interface_reset(TB_Wb_interface * tb) {
-  Vtb_wb_interface * core = tb->core;
-  core->testcase = T_RESET;
-
-  // The following actions are performed in this test :
-  //    tick 0. Reset (core is in reset)
-  //    tick 1. Still in reset (core is still in reset)
-  
-  //=================================
-  //      Tick (0)
-  
-  tb->reset();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->rst_i = 1;
-
-  //=================================
-  //      Tick (1)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_wishbone, (core->wb_ack_o == 0));
-  tb->check(COND_output,   (core->read_o   == 0) &&
-                           (core->write_o  == 0));
-
-  //=================================
-  //      Tick (1)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_wishbone, (core->wb_ack_o == 0));
-  tb->check(COND_output,   (core->read_o   == 0) &&
-                           (core->write_o  == 0));
-
-  //`````````````````````````````````
-  //      Formal Checks 
-  
-  CHECK("tb_wb_interface.reset.01",
-      tb->conditions[COND_output],
-      "Failed to implement the output logic", tb->err_cycles[COND_output]);
-
-  CHECK("tb_wb_interface.reset.02",
-      tb->conditions[COND_wishbone],
-      "Failed to implement the wishbone protocol", tb->err_cycles[COND_wishbone]);
-}
-
-void tb_wb_interface_read(TB_Wb_interface * tb) {
-  Vtb_wb_interface * core = tb->core;
-  core->testcase = T_READ;
-
-  //=================================
-  //      Tick (0)
-  
-  tb->reset();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  tb->check(COND_output, (core->read_o == 0) &&
-                         (core->write_o == 0));
-  
-  uint32_t addr = rand();
-  tb->read(addr);
-
-  // Async logic
-  core->eval();
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_output, (core->read_o == 1) &&
-                         (core->addr_o == (addr & 0xFF)) &&
-                         (core->write_o == 0));
-
-  //=================================
-  //      Tick (1)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  tb->_nop();
-  core->wb_cyc_i = 1;
-
-  uint32_t data = rand();
-  core->read_data_i = data;
-
-  // Async logic
-  core->eval();
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_wishbone, (core->wb_ack_o == 1) &&
-                           (core->wb_dat_o == data));
-  tb->check(COND_output, (core->read_o == 0) &&
-                         (core->write_o == 0));
-
-  //=================================
-  //      Tick (2)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_wishbone, (core->wb_ack_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->wb_cyc_i = 0;
-
-  core->read_data_i = 0;
-
-  //=================================
-  //      Tick (3)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Formal Checks 
-  
-  CHECK("tb_wb_interface.read.01",
-      tb->conditions[COND_output],
-      "Failed to implement the output logic", tb->err_cycles[COND_output]);
-
-  CHECK("tb_wb_interface.read.02",
-      tb->conditions[COND_wishbone],
-      "Failed to implement the wishbone protocol", tb->err_cycles[COND_wishbone]);
-}
-
-void tb_wb_interface_write(TB_Wb_interface * tb) {
-  Vtb_wb_interface * core = tb->core;
-  core->testcase = T_WRITE;
-
-  //=================================
-  //      Tick (0)
-  
-  tb->reset();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  tb->check(COND_output, (core->read_o == 0) &&
-                           (core->write_o == 0));
-  
-  uint32_t addr = rand();
-  uint32_t data = rand();
-  tb->write(addr, data);
-
-  // Async logic
-  core->eval();
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_output, (core->read_o == 0) &&
-                         (core->addr_o == (addr & 0xFF)) &&
-                         (core->write_o == 1) &&
-                         (core->write_data_o == data));
-
-  //=================================
-  //      Tick (1)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  tb->_nop();
-  core->wb_cyc_i = 1;
-
-  // Async logic
-  core->eval();
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_wishbone, (core->wb_ack_o == 1));
-  tb->check(COND_output, (core->read_o == 0) &&
-                         (core->write_o == 0));
-
-  //=================================
-  //      Tick (2)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_wishbone, (core->wb_ack_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->wb_cyc_i = 0;
-
-  //=================================
-  //      Tick (3)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Formal Checks 
-  
-  CHECK("tb_wb_interface.write.01",
-      tb->conditions[COND_output],
-      "Failed to implement the output logic", tb->err_cycles[COND_output]);
-
-  CHECK("tb_wb_interface.write.02",
-      tb->conditions[COND_wishbone],
-      "Failed to implement the wishbone protocol", tb->err_cycles[COND_wishbone]);
-}
-
-int main(int argc, char ** argv, char ** env) {
-  srand(time(NULL));
-  Verilated::traceEverOn(true);
-
-  bool verbose = parse_verbose(argc, argv);
-  verbose=1;
-
-  TB_Wb_interface * tb = new TB_Wb_interface;
-  tb->open_trace("waves/wb_interface.vcd");
-  tb->open_testdata("testdata/wb_interface.csv");
-  tb->set_debug_log(verbose);
-  tb->init_conditions(__CondIdEnd);
-
-  /************************************************************/
-
-  tb_wb_interface_reset(tb);
-  tb_wb_interface_read(tb);
-  tb_wb_interface_write(tb);
-
-  /************************************************************/
-
-  printf("[WB_INTERFACE]: ");
-  if(tb->success) {
-    printf("Done\n");
-  } else {
-    printf("Failed\n");
-  }
-
-  delete tb;
-  exit(EXIT_SUCCESS);
-}
diff --git a/tests/benches/wb_interface/tb_wb_interface.sv b/tests/benches/wb_interface/tb_wb_interface.sv
deleted file mode 100644
index 775695a..0000000
--- a/tests/benches/wb_interface/tb_wb_interface.sv
+++ /dev/null
@@ -1,74 +0,0 @@
-/*           __        _
- *  ________/ /  ___ _(_)__  ___
- * / __/ __/ _ \/ _ `/ / _ \/ -_)
- * \__/\__/_//_/\_,_/_/_//_/\__/
- * 
- * Copyright (C) Clément Chaine
- * This file is part of ECAP5-DWBUART <https://github.com/ecap5/ECAP5-DWBUART>
- *
- * ECAP5-DWBUART is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * ECAP5-DWBUART is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with ECAP5-DWBUART.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-module tb_wb_interface
-(
-  input   int          testcase,
-
-  input   logic         clk_i,
-  input   logic         rst_i,
-
-  //=================================
-  //    Memory interface
-
-  input   logic[31:0]  wb_adr_i,
-  output  logic[31:0]  wb_dat_o,
-  input   logic[31:0]  wb_dat_i,
-  input   logic        wb_we_i,
-  input   logic[3:0]   wb_sel_i,
-  input   logic        wb_stb_i,
-  output  logic        wb_ack_o,
-  input   logic        wb_cyc_i,
-  output  logic        wb_stall_o,
-
-  //=================================
-  //    Output interface
-
-  output  logic[7:0]   addr_o,
-  output  logic        read_o,
-  input   logic[31:0]  read_data_i,
-  output  logic        write_o,
-  output  logic[31:0]  write_data_o
-);
-
-wb_interface dut (
-  .clk_i           (clk_i),
-  .rst_i           (rst_i),
-
-  .wb_adr_i   (wb_adr_i),
-  .wb_dat_o   (wb_dat_o),
-  .wb_dat_i   (wb_dat_i),
-  .wb_we_i    (wb_we_i),
-  .wb_sel_i   (wb_sel_i),
-  .wb_stb_i   (wb_stb_i),
-  .wb_ack_o   (wb_ack_o),
-  .wb_cyc_i   (wb_cyc_i),
-  .wb_stall_o (wb_stall_o),
-
-  .addr_o       (addr_o),
-  .read_o       (read_o),
-  .read_data_i  (read_data_i),
-  .write_o      (write_o),
-  .write_data_o (write_data_o)
-);
-
-endmodule // tb_wb_interface

From b9122a30847696260edac189cd34114c0c5b5625 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Cl=C3=A9ment=20Chaine?= <clement.chaine25@gmail.com>
Date: Wed, 26 Nov 2025 19:47:49 +0100
Subject: [PATCH 03/15] Use cmake interface libraries

---
 .github/workflows/ci-config.yml |  6 ++-
 CMakeLists.txt                  | 95 ++++++++++++++++++---------------
 cmake/dependency.cmake          | 67 ++++++++++++++++-------
 tests/CMakeLists.txt            | 40 +++++++-------
 4 files changed, 125 insertions(+), 83 deletions(-)

diff --git a/.github/workflows/ci-config.yml b/.github/workflows/ci-config.yml
index 957338b..1643704 100644
--- a/.github/workflows/ci-config.yml
+++ b/.github/workflows/ci-config.yml
@@ -24,7 +24,11 @@ jobs:
     - uses: actions/checkout@v4.1.1
 
     - name: Configure CMake
-      run: cmake -B ${{github.workspace}}/build -GNinja
+      run: cmake -B ${{github.workspace}}/build -GNinja -DCMAKE_BUILD_TYPE=${{env.BUILD_TYPE}} 2>&1 | tee ${{github.workspace}}/cmake.log
+
+    - name: Check versions
+      if: github.event.pull_request.base.ref == 'main'
+      run: (! grep -e "Using .* with unreleased version" ${{github.workspace}}/cmake.log)
 
     - name: Cache build directory
       if: always()
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 747e8ef..40ea049 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -19,16 +19,15 @@
 # You should have received a copy of the GNU General Public License
 # along with ECAP5-DWBUART.  If not, see <http://www.gnu.org/licenses/>.
 
-cmake_minimum_required(VERSION 3.12)
+cmake_minimum_required(VERSION 3.21)
 include(FetchContent)
 
-project(ECAP5_DWBUART VERSION 1.0.0)
+project(ECAP5_DWBUART)
 
 set(CMAKE_MODULE_PATH "${CMAKE_CURRENT_LIST_DIR}/cmake")
 set(CMAKE_PREFIX_PATH "${CMAKE_CURRENT_LIST_DIR}/cmake")
 
 # Create python virtual env
-message(STATUS "Creating python venv")
 set(VENV_DIR ${CMAKE_BINARY_DIR}/venv)
 if(NOT EXISTS "${VENV_DIR}")
   find_package(Python3 COMPONENTS Interpreter)
@@ -41,54 +40,66 @@ find_package(Python3 COMPONENTS Interpreter Development)
 
 # Dependencies
 
-message(STATUS "Collecting dependencies")
 include(${CMAKE_CURRENT_LIST_DIR}/cmake/dependency.cmake)
 
-add_dependency(ECAP5_TREQ 
-  GIT ecap5/ecap5-treq
-  TAG tags/v2.3.1
-  BINARY ecap5-treq)
-
-add_dependency(ECAP5_DTESTLIB
-  GIT ecap5/ecap5-dtestlib
-  TAG release/v1.1.0)
-
-add_dependency(ECAP5_DWBMMSC
-  GIT ecap5/ecap5-dwbmmsc
-  TAG release/v1.0.0)
-
-add_dependency(sphinx-cmake
+add_dependency(
   GIT ecap5/sphinx-cmake
   TAG tags/v1.0.1)
 
-add_dependency(verilator-cmake
+add_dependency(
   GIT ecap5/verilator-cmake
   TAG tags/v1.0.1)
 
-add_dependency(oss-cad-suite-cmake
-  GIT ecap5/oss-cad-suite-cmake
-  TAG tags/v1.0.0)
-
-# Configure dependencies
-
-include(${verilator_cmake_SOURCE_DIR}/cmake/verilator-config.cmake)
-include(${ecap5_treq_SOURCE_DIR}/config.cmake)
-list(APPEND CMAKE_MODULE_PATH "${sphinx_cmake_SOURCE_DIR}/cmake")
-include(${oss_cad_suite_cmake_SOURCE_DIR}/cmake/oss-cad-suite-config.cmake)
-include(${ecap5_dtestlib_SOURCE_DIR}/cmake/testbench.cmake)
-include(${ecap5_dtestlib_SOURCE_DIR}/cmake/lint.cmake)
-
-# Include subdirectories
+add_dependency(
+  GIT ecap5/ecap5-treq
+  TAG release/v3.0.0
+  BINARY ecap5-treq)
 
-add_subdirectory(docs)
-add_subdirectory(tests)
+add_dependency(
+  GIT ecap5/oss-cad-suite-cmake
+  TAG release/v2.0.0)
 
-# Synthesis
+add_dependency(
+  GIT ecap5/ecap5-dtestlib
+  TAG release/v1.1.0)
 
-add_synthesis_target(
-  SOURCES ${CMAKE_CURRENT_LIST_DIR}/src/* ${ecap5_dwbmmsc_SOURCE_DIR}/src/*
-  TOP_MODULE ecap5_dwbuart
-  TARGET_FPGA ecp5
-  OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/synth.json)
+add_dependency(
+  GIT ecap5/ecap5-dwbmmsc
+  TAG release/v1.0.0)
 
-add_custom_target(synth DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/synth.json)
+# Define an interface library
+add_library(ecap5_dwbuart INTERFACE)
+target_sources(ecap5_dwbuart INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/src/ecap5_dwbuart.sv
+  ${CMAKE_CURRENT_LIST_DIR}/src/rx_frontend.sv
+  ${CMAKE_CURRENT_LIST_DIR}/src/tx_frontend.sv
+)
+target_link_libraries(ecap5_dwbuart INTERFACE 
+  ecap5_dwbmmsc
+)
+
+if(PROJECT_IS_TOP_LEVEL)
+  # Configure dependencies
+
+  include(${ecap5_verilator_cmake_SOURCE_DIR}/cmake/verilator-config.cmake)
+  include(${ecap5_ecap5_treq_SOURCE_DIR}/config.cmake)
+  list(APPEND CMAKE_MODULE_PATH "${ecap5_sphinx_cmake_SOURCE_DIR}/cmake")
+  include(${ecap5_oss_cad_suite_cmake_SOURCE_DIR}/cmake/oss-cad-suite-config.cmake)
+  include(${ecap5_ecap5_dtestlib_SOURCE_DIR}/cmake/testbench.cmake)
+  include(${ecap5_ecap5_dtestlib_SOURCE_DIR}/cmake/lint.cmake)
+
+  # Include subdirectories
+
+  add_subdirectory(docs)
+  add_subdirectory(tests)
+
+  # Synthesis
+
+  add_synthesis_target(
+    LIB        ecap5_dwbuart
+    TOP_MODULE ecap5_dwbuart
+    TARGET_FPGA ecp5
+    OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/synth.json)
+
+  add_custom_target(synth DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/synth.json)
+endif()
diff --git a/cmake/dependency.cmake b/cmake/dependency.cmake
index 52fb521..60e913a 100644
--- a/cmake/dependency.cmake
+++ b/cmake/dependency.cmake
@@ -1,26 +1,57 @@
-macro(add_dependency id)
+macro(add_dependency)
   cmake_parse_arguments(ARG ""
                             "GIT;TAG;BINARY"
                             ""
                             ${ARGN})
-  string(MAKE_C_IDENTIFIER "${id}" name)
-  string(TOLOWER "${name}" name)
-
-  FetchContent_Declare(${name}
-    GIT_REPOSITORY https://github.com/${ARG_GIT}
-    GIT_TAG ${ARG_TAG}
-    SOURCE_SUBDIR __none__
-  )
-  FetchContent_MakeAvailable(${name})
-
-  if(NOT DEFINED ${name}_EXECUTABLE)
-    if(EXISTS "${${name}_SOURCE_DIR}/pyproject.toml")
-      message(STATUS "Configuring ${name}")
-      execute_process(COMMAND ${Python3_EXECUTABLE} -m pip install ${${name}_SOURCE_DIR} OUTPUT_QUIET RESULT_VARIABLE rv)
-      if("${rv}" STREQUAL "0")
-        set(${name}_EXECUTABLE ${VENV_DIR}/bin/${ARG_BINARY} CACHE STRING "path to the ${name} executable")
+  set(REPOSITORY_URL https://github.com/${ARG_GIT})
+
+  # Create a unique identifier for the dependency
+  string(MAKE_C_IDENTIFIER "${ARG_GIT}" DEPENDENCY_ID)
+  string(TOLOWER "${DEPENDENCY_ID}" DEPENDENCY_ID)
+
+  get_property(IS_DEPENDENCY_PRESENT GLOBAL PROPERTY ${DEPENDENCY_ID}_VERSION SET)
+
+  # Check if the dependency is already present
+  if(${IS_DEPENDENCY_PRESENT})
+    get_property(${DEPENDENCY_ID}_VERSION GLOBAL PROPERTY ${DEPENDENCY_ID}_VERSION)
+    # Check that the version is the same
+    if(NOT ${DEPENDENCY_ID}_VERSION STREQUAL ARG_TAG)
+      message(FATAL_ERROR "Dependency ${ARG_GIT} version mismatched\n\t${${DEPENDENCY_ID}_VERSION} != ${ARG_TAG}")
+    endif()
+  else()
+    message(STATUS "Configuring ${ARG_GIT}")
+
+    # Define the version
+    set_property(GLOBAL PROPERTY ${DEPENDENCY_ID}_VERSION ${ARG_TAG})
+
+    # Check if released version
+    if(CMAKE_BUILD_TYPE STREQUAL "Release")
+      if(NOT ${ARG_TAG} MATCHES "^tags/.*")
+        message(WARNING "Using ${ARG_GIT} with unreleased version ${ARG_TAG}")
       endif()
     endif()
-  endif()
 
+    # Fetch the repository
+    FetchContent_Declare(${DEPENDENCY_ID}
+      GIT_REPOSITORY ${REPOSITORY_URL}
+      GIT_TAG ${ARG_TAG}
+      SOURCE_SUBDIR __none__
+    )
+    FetchContent_MakeAvailable(${DEPENDENCY_ID})
+
+    # Add cmake build if it exists
+    if(EXISTS "${${DEPENDENCY_ID}_SOURCE_DIR}/CMakeLists.txt")
+      add_subdirectory(${${DEPENDENCY_ID}_SOURCE_DIR} ${${DEPENDENCY_ID}_SOURCE_DIR}/../${DEPENDENCY_ID}-build)
+    endif()
+
+    # Handle python executable if it exists
+    if(NOT DEFINED ${DEPENDENCY_ID}_EXECUTABLE)
+      if(EXISTS "${${DEPENDENCY_ID}_SOURCE_DIR}/pyproject.toml")
+        execute_process(COMMAND ${Python3_EXECUTABLE} -m pip install -e ${${DEPENDENCY_ID}_SOURCE_DIR} OUTPUT_QUIET RESULT_VARIABLE rv)
+        if("${rv}" STREQUAL "0")
+          set(${DEPENDENCY_ID}_EXECUTABLE ${VENV_DIR}/bin/${ARG_BINARY} CACHE STRING "path to the ${DEPENDENCY_ID} executable")
+        endif()
+      endif()
+    endif()
+  endif()
 endmacro()
diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt
index 2f63a84..370b5f0 100644
--- a/tests/CMakeLists.txt
+++ b/tests/CMakeLists.txt
@@ -22,43 +22,39 @@
 # Bench parent directory
 set(BENCH_DIR ${CMAKE_CURRENT_SOURCE_DIR}/benches/)
 # C++ bench include directory
-set(TEST_INCLUDE_DIR ${ecap5_dtestlib_SOURCE_DIR}/include)
-# HDL source directories
-set(SRC_DIRS ${CMAKE_SOURCE_DIR}/src/ ${ecap5_dwbmmsc_SOURCE_DIR}/src/)
-# HDL library directories
-set(LIBS_DIR ${ecap5_dtestlib_SOURCE_DIR}/src/)
+set(TEST_INCLUDE_DIRS ${ecap5_ecap5_dtestlib_SOURCE_DIR}/include)
 # Bench CSV output directory
-set(TESTDATA_DIR ${CMAKE_CURRENT_BINARY_DIR}/testdata/)
+set(TESTDATA_DIR ${CMAKE_CURRENT_BINARY_DIR}/)
 
 # Lint
 add_lint_target(
   TARGET lint
-  SRC_DIRS ${SRC_DIRS}
+  LIB    ecap5_dwbmmsc
 )
 
 # Add testbenches
 add_testbench(
-  MODULE       rx_frontend
-  BENCH_DIR    ${BENCH_DIR}
-  LIBS_DIR     ${LIBS_DIR}
-  TESTDATA_DIR ${TESTDATA_DIR}
-  SRC_DIRS     ${SRC_DIRS} 
+  MODULE            rx_frontend
+  LIBS              ecap5_dwbuart
+  BENCH_DIR         ${BENCH_DIR}
+  TESTDATA_DIR      ${TESTDATA_DIR}
+  TEST_INCLUDE_DIRS ${TEST_INCLUDE_DIRS}
 )
 
 add_testbench(
-  MODULE       tx_frontend
-  BENCH_DIR    ${BENCH_DIR}
-  LIBS_DIR     ${LIBS_DIR}
-  TESTDATA_DIR ${TESTDATA_DIR}
-  SRC_DIRS     ${SRC_DIRS} 
+  MODULE            tx_frontend
+  LIBS              ecap5_dwbuart
+  BENCH_DIR         ${BENCH_DIR}
+  TESTDATA_DIR      ${TESTDATA_DIR}
+  TEST_INCLUDE_DIRS ${TEST_INCLUDE_DIRS}
 )
 
 add_testbench(
-  MODULE       ecap5_dwbuart
-  BENCH_DIR    ${BENCH_DIR}
-  LIBS_DIR     ${LIBS_DIR}
-  TESTDATA_DIR ${TESTDATA_DIR}
-  SRC_DIRS     ${SRC_DIRS} 
+  MODULE            ecap5_dwbuart
+  LIBS              ecap5_dwbuart
+  BENCH_DIR         ${BENCH_DIR}
+  TESTDATA_DIR      ${TESTDATA_DIR}
+  TEST_INCLUDE_DIRS ${TEST_INCLUDE_DIRS}
 )
 
 # Main targets

From 92564cff238f64a5efb85faced82cac8b12164c2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Cl=C3=A9ment=20Chaine?= <clement.chaine25@gmail.com>
Date: Sat, 29 Nov 2025 09:52:46 +0100
Subject: [PATCH 04/15] Add support for near arbitrary baudrate

---
 docs/src/spec/2_overall-description.rst       |    4 +
 docs/src/spec/content/uart_cr.rst             |   10 +-
 src/ecap5_dwbuart.sv                          |   16 +-
 src/rx_frontend.sv                            |    8 +-
 src/tx_frontend.sv                            |   67 +-
 .../ecap5_dwbuart/tb_ecap5_dwbuart.cpp        |   14 +-
 .../benches/ecap5_dwbuart/tb_ecap5_dwbuart.sv |    2 +-
 tests/benches/rx_frontend/tb_rx_frontend.cpp  |   32 +-
 tests/benches/rx_frontend/tb_rx_frontend.sv   |    4 +-
 tests/benches/tx_frontend/tb_tx_frontend.cpp  | 2603 ++++++++++-------
 tests/benches/tx_frontend/tb_tx_frontend.sv   |    4 +-
 11 files changed, 1634 insertions(+), 1130 deletions(-)

diff --git a/docs/src/spec/2_overall-description.rst b/docs/src/spec/2_overall-description.rst
index 37be63c..55fbb5e 100644
--- a/docs/src/spec/2_overall-description.rst
+++ b/docs/src/spec/2_overall-description.rst
@@ -42,6 +42,10 @@ Configuration
 
    The baud rate of the peripheral shall be software-configurable.
 
+.. requirement:: U_BAUD_RATE_02
+
+   The following baudrates shall be tested to be within 2% tolerance : 4800, 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600, 1000000, 2000000, 3000000.
+
 .. requirement:: U_PARITY_BIT_01
 
    The parity bit of the peripheral shall be software-configurable.
diff --git a/docs/src/spec/content/uart_cr.rst b/docs/src/spec/content/uart_cr.rst
index 3768b4e..a3aa219 100644
--- a/docs/src/spec/content/uart_cr.rst
+++ b/docs/src/spec/content/uart_cr.rst
@@ -14,7 +14,7 @@ UART_CR contains the control for selecting the UART baudrate, parity, size and s
             { "name": "S", "bits": 1},
             { "name": "DS", "bits": 1},
             { "name": "reserved", "bits": 12, "type": 1},
-            { "name": "CLK_DIV", "bits": 16}
+            { "name": "ACC_INCR", "bits": 16}
         ]
 
 |
@@ -28,10 +28,10 @@ UART_CR contains the control for selecting the UART baudrate, parity, size and s
     - Description
 
   * - 31-16
-    - CLK_DIV
-    - *Clock Divider/Baud Rate selector*
+    - ACC_INCR
+    - *Accumulator increment/Baudrate selector*
 
-      The specified clock divider determines the baud rate with the formula Baud Rate = Freq / CLK_DIV.
+      The specified accumulator increment determines the baud rate with the formula ACC_INCR = round(baudrate * 2^15 / freq).
   * - 15-4
     - reserved
     - *This field is reserved.*
@@ -50,7 +50,7 @@ UART_CR contains the control for selecting the UART baudrate, parity, size and s
        
       0 |tab| 1 stop bit
 
-      2 |tab| 1.5 stop bits
+      1 |tab| 2 stop bits
   * - 1-0
     - P
     - *Parity bit selector*
diff --git a/src/ecap5_dwbuart.sv b/src/ecap5_dwbuart.sv
index e2c4f90..8b275a7 100644
--- a/src/ecap5_dwbuart.sv
+++ b/src/ecap5_dwbuart.sv
@@ -83,7 +83,7 @@ logic tx_transmit_d, tx_transmit_q,
 /*        Memory mapped registers        */
 /*****************************************/
 
-logic[15:0] cr_clk_div_d, cr_clk_div_q;
+logic[15:0] cr_acc_incr_d, cr_acc_incr_q;
 logic       cr_ds_d, cr_ds_q,
             cr_s_d, cr_s_q;
 logic[1:0]  cr_p_d, cr_p_q;
@@ -105,7 +105,7 @@ rx_frontend #(
 ) rx_frontend_inst (
   .clk_i (clk_i),   .rst_i (frontend_rst),
 
-  .cr_clk_div_i   (cr_clk_div_q),
+  .cr_acc_incr_i   (cr_acc_incr_q),
   .cr_ds_i        (cr_ds_q),
   .cr_s_i         (cr_s_q),
   .cr_p_i         (cr_p_q),
@@ -124,7 +124,7 @@ tx_frontend #(
 ) tx_frontend_inst (
   .clk_i (clk_i),   .rst_i (frontend_rst),
 
-  .cr_clk_div_i   (cr_clk_div_q),
+  .cr_acc_incr_i   (cr_acc_incr_q),
   .cr_ds_i        (cr_ds_q),
   .cr_s_i         (cr_s_q),
   .cr_p_i         (cr_p_q),
@@ -153,7 +153,7 @@ ecap5_dwbmmsc wb_interface_inst (
 );
 
 always_comb begin : register_access
-  cr_clk_div_d = cr_clk_div_q;
+  cr_acc_incr_d = cr_acc_incr_q;
   cr_ds_d      = cr_ds_q;
   cr_s_d       = cr_s_q;
   cr_p_d       = cr_p_q;
@@ -171,7 +171,7 @@ always_comb begin : register_access
   mem_read_data_d = 0;
   case(mem_addr[7:2])
     UART_SR:   mem_read_data_d = {27'b0, sr_pe_q, sr_fe_q, sr_rxoe_q, sr_txe_q, sr_rxne_q};
-    UART_CR:   mem_read_data_d = {cr_clk_div_q, 12'b0, cr_s_q, cr_p_q, cr_ds_q};
+    UART_CR:   mem_read_data_d = {cr_acc_incr_q, 12'b0, cr_s_q, cr_p_q, cr_ds_q};
     UART_RXDR: mem_read_data_d = {24'b0, rxdr_rxd_q};
     default:   mem_read_data_d = '0;
   endcase
@@ -180,7 +180,7 @@ always_comb begin : register_access
   if(mem_write) begin
     case(mem_addr[7:2])
       UART_CR: begin
-        cr_clk_div_d = mem_write_data[31:16];
+        cr_acc_incr_d = mem_write_data[31:16];
         cr_ds_d = mem_write_data[3];
         cr_s_d = mem_write_data[2];
         cr_p_d = mem_write_data[1:0];
@@ -237,7 +237,7 @@ end
 
 always_ff @(posedge clk_i) begin
   if(rst_i) begin
-    cr_clk_div_q <= '0;
+    cr_acc_incr_q <= '0;
     cr_ds_q <= 0;
     cr_s_q <= 0;
     cr_p_q <= '0;
@@ -255,7 +255,7 @@ always_ff @(posedge clk_i) begin
 
     mem_read_data_q <= '0;
   end else begin
-    cr_clk_div_q <= cr_clk_div_d;
+    cr_acc_incr_q <= cr_acc_incr_d;
     cr_ds_q <= cr_ds_d;
     cr_s_q <= cr_s_d;
     cr_p_q <= cr_p_d;
diff --git a/src/rx_frontend.sv b/src/rx_frontend.sv
index a5efee9..9c1da01 100644
--- a/src/rx_frontend.sv
+++ b/src/rx_frontend.sv
@@ -27,7 +27,7 @@ module rx_frontend #(
   input   logic         clk_i,
   input   logic         rst_i,
 
-  input   logic[15:0]   cr_clk_div_i,
+  input   logic[15:0]   cr_acc_incr_i,
   input   logic         cr_ds_i,
   input   logic[1:0]    cr_p_i,
   input   logic         cr_s_i,
@@ -127,7 +127,7 @@ always_comb begin : sampling
         // It takes one cycle for this counter to be decremented (switch to START state)
         // It takes on cycle for logic to detect this counter is null
         // The counter is therefore initialized to half the baud interval - 2
-        half_baud_cnt_d = {1'b0, cr_clk_div_i[15:1]} - 2;
+        half_baud_cnt_d = {1'b0, cr_acc_incr_i[15:1]} - 2;
       end
     end
     START: begin
@@ -136,7 +136,7 @@ always_comb begin : sampling
       if(half_baud_cnt_q == '0) begin
         // It takes one cycle for logic to detect this counter is null
         // The counter is therefore initialized to the baud interval - 1
-        baud_cnt_d = cr_clk_div_i - 1;
+        baud_cnt_d = cr_acc_incr_i - 1;
         // Initialize the frame size ring counter
         frame_bit_cnt_d[0] = 1'b1;
         // Initialize the parity bit with the parity configuration bit
@@ -151,7 +151,7 @@ always_comb begin : sampling
         //   2. decrement the frame bit counter
         //   3. sample the input
         //   4. update the computed parity
-        baud_cnt_d = cr_clk_div_i - 1;
+        baud_cnt_d = cr_acc_incr_i - 1;
         frame_bit_cnt_d = {frame_bit_cnt_d[MAX_FRAME_SIZE-1:0], 1'b0};
         frame_d = {uart_rx_qqq, frame_q[10:1]};
         parity_d = parity_q ^ (uart_rx_qqq & (~data_bit_cnt_done_q));
diff --git a/src/tx_frontend.sv b/src/tx_frontend.sv
index 2fd24fb..74794ef 100644
--- a/src/tx_frontend.sv
+++ b/src/tx_frontend.sv
@@ -27,7 +27,7 @@ module tx_frontend #(
   input   logic         clk_i,
   input   logic         rst_i,
 
-  input   logic[15:0]   cr_clk_div_i,
+  input   logic[15:0]   cr_acc_incr_i,
   input   logic         cr_ds_i,
   input   logic[1:0]    cr_p_i,
   input   logic         cr_s_i,
@@ -53,9 +53,14 @@ typedef enum {
 } state_t;
 state_t state_d, state_q;
 
-logic[15:0] baud_cnt_d, baud_cnt_q;
+// Baudrate accumulator
+logic[16:0] baud_acc_d, baud_acc_q;
+logic baud_acc_overflow;
 
+// Frame bit counter
 logic[$size(dr_i)-1:0] bit_cnt_d, bit_cnt_q;
+
+// Data shift-register
 logic[$size(dr_i)-1:0] dr_d, dr_q;
 
 logic parity_d, parity_q;
@@ -70,24 +75,40 @@ logic done_d, done_q;
 
 /*****************************************/
 
+always_comb begin : baudrate_generation
+  // Reset the baud accumulator when in the IDLE state
+  if(state_q == IDLE && transmit_i) begin
+    baud_acc_d = 0;
+  end else begin
+    // Increment the accumulator
+    // In this case, baud_acc_q[15] is not used as we want this bit
+    // to be set to one only when the increment overflows.
+    // In that case, on the next cycle this bit is not used but the 
+    // remaining bits are.
+    baud_acc_d = {1'b0, baud_acc_q[15:0]} + {1'b0, cr_acc_incr_i};
+  end
+  baud_acc_overflow = baud_acc_d[16];
+end
+
 always_comb begin : state_machine
   state_d = state_q;
 
   case(state_q)
     IDLE: begin
+      // If a transmit is initiated
       if(transmit_i) begin
         state_d = START;
       end 
     end
     START: begin
-      // Wait for a baud interval
-      if(baud_cnt_q == '0) begin
+      // Wait for a baud interval (1-bit)
+      if(baud_acc_overflow) begin
         state_d = DATA;
       end
     end
     DATA: begin
-      // Wait for the end of the last baud interval
-      if(baud_cnt_q == '0 && bit_cnt_q[0]) begin
+      // Wait for the end of the last baud interval (all data-bits)
+      if(baud_acc_overflow && bit_cnt_q[0]) begin
         // Bypass the parity bit based on configuration
         if(cr_p_i == '0) begin
           state_d = STOP;
@@ -97,14 +118,14 @@ always_comb begin : state_machine
       end
     end
     PARITY: begin
-      // Wait for a baud interval
-      if(baud_cnt_q == '0) begin
+      // Wait for a baud interval (1-bit)
+      if(baud_acc_overflow) begin
         state_d = STOP;
       end
     end
     STOP: begin
-      // Wait for the last baud interval
-      if(baud_cnt_q == '0 && bit_cnt_q[0]) begin
+      // Wait for the last baud interval (n stop bits)
+      if(baud_acc_overflow && bit_cnt_q[0]) begin
         state_d = IDLE;
       end
     end
@@ -117,20 +138,16 @@ always_comb begin : transmit
 
   uart_tx_d = 1;
 
-  // Update the baud interval counter
-  if(baud_cnt_q == '0 || (state_q == IDLE && transmit_i)) begin
-    baud_cnt_d = cr_clk_div_i - 1;
-  end else begin
-    baud_cnt_d = baud_cnt_q - 1;
-  end
-
   bit_cnt_d = bit_cnt_q;
   parity_d = parity_q;
 
   case(state_q)
     IDLE: begin
+      // If a transmit is initiated
       if(transmit_i) begin
+        // Initialize the number of bits to send
         bit_cnt_d = cr_ds_i ? (1 << 7) : (1 << 6);
+        // Initialize the data shift register
         dr_d = dr_i;
         // Initialize the parity
         parity_d = cr_p_i[0];
@@ -142,10 +159,11 @@ always_comb begin : transmit
     DATA: begin
       uart_tx_d = dr_q[0];
 
-      // Wait for the end of a baud interval
-      if(baud_cnt_q == '0) begin
+      // After each data bit is sent (one baud period)
+      if(baud_acc_overflow) begin
         // Updates the number of remaining data bits
         bit_cnt_d = {1'b0, bit_cnt_q[$size(dr_i)-1:1]};
+        // Shift the data register
         dr_d = {1'b0, dr_q[$size(dr_i)-1:1]};
 
         // Update the parity with the sent bit
@@ -163,8 +181,9 @@ always_comb begin : transmit
     STOP: begin
       uart_tx_d = 1'b1;
 
-      // Update the number of remaining stop bits
-      if(baud_cnt_q == '0) begin
+      // After each stop bit is sent (one baud period)
+      if(baud_acc_overflow) begin
+        // Update the number of remaining stop bits
         bit_cnt_d = {1'b0, bit_cnt_q[$size(dr_i)-1:1]};
       end
     end
@@ -178,7 +197,7 @@ always_comb begin : done
   //   - in the stop STATE
   //   - at the end of a baud interval
   //   - during the last stop bit
-  if(state_q == STOP && baud_cnt_q == '0 && bit_cnt_q[0]) begin
+  if(state_q == STOP && baud_acc_overflow && bit_cnt_q[0]) begin
     done_d = 1;
   end
 end
@@ -188,7 +207,7 @@ always_ff @(posedge clk_i) begin
     state_q <= IDLE;
 
     dr_q <= '0;
-    baud_cnt_q <= 0;
+    baud_acc_q <= 0;
     bit_cnt_q <= 0;
     parity_q <= 0;
 
@@ -200,7 +219,7 @@ always_ff @(posedge clk_i) begin
     dr_q <= dr_d;
 
     // baudrate counter used to sample the serial signal
-    baud_cnt_q <= baud_cnt_d;
+    baud_acc_q <= baud_acc_d;
 
     // Computed parity
     parity_q <= parity_d;
diff --git a/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.cpp b/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.cpp
index ffa20b9..0c8b5a3 100644
--- a/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.cpp
+++ b/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.cpp
@@ -116,7 +116,7 @@ class TB_Ecap5_dwbuart : public Testbench<Vtb_ecap5_dwbuart> {
 
   uint32_t uart_cr() {
     uint32_t reg = 0;
-    reg |= core->tb_ecap5_dwbuart->dut->cr_clk_div_q << 16;
+    reg |= core->tb_ecap5_dwbuart->dut->cr_acc_incr_q << 16;
     reg |= core->tb_ecap5_dwbuart->dut->cr_ds_q << 3;
     reg |= core->tb_ecap5_dwbuart->dut->cr_s_q << 2;
     reg |= core->tb_ecap5_dwbuart->dut->cr_p_q;
@@ -131,28 +131,28 @@ class TB_Ecap5_dwbuart : public Testbench<Vtb_ecap5_dwbuart> {
     return core->tb_ecap5_dwbuart->dut->txdr_txd_q;
   }
 
-  void send(uint32_t data, uint32_t clk_div, uint8_t ds, uint8_t p, uint8_t s, uint8_t inject_pe, uint8_t inject_fe) {
+  void send(uint32_t data, uint32_t acc_incr, uint8_t ds, uint8_t p, uint8_t s, uint8_t inject_pe, uint8_t inject_fe) {
     // Start bit
     this->core->uart_rx_i = 0;
-    this->n_tick(clk_div);
+    this->n_tick(acc_incr);
     // Data bits
     uint8_t num_data_bits = ds ? 8 : 7;
     uint8_t parity = p & 0x1;
     for(int i = 0; i < num_data_bits; i++) {
       this->core->uart_rx_i = (data >> i) & 0x1;
       parity ^= (data >> i) & 0x1;
-      this->n_tick(clk_div);
+      this->n_tick(acc_incr);
     }
     // Parity bits
     if(p) {
       this->core->uart_rx_i = inject_pe ? (parity ^ 1) : 0; 
-      this->n_tick(clk_div);
+      this->n_tick(acc_incr);
     }
     // Stop bits
     uint8_t num_stop_bits = s ? 2 : 1;
     for(int i = 0; i < num_stop_bits; i++) {
       this->core->uart_rx_i = !inject_fe;
-      this->n_tick(clk_div);
+      this->n_tick(acc_incr);
     }
   }
 };
@@ -388,7 +388,7 @@ void tb_ecap5_dwbuart_write_txdr(TB_Ecap5_dwbuart * tb) {
   //=================================
   //      Tick (6-7)
   
-  // Wait half clk_div
+  // Wait half acc_incr
   tb->n_tick(2);
 
   //`````````````````````````````````
diff --git a/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.sv b/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.sv
index fdb9085..4cad746 100644
--- a/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.sv
+++ b/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.sv
@@ -84,7 +84,7 @@ public -module "ecap5_dwbuart" -var "rx_valid"
 public -module "ecap5_dwbuart" -var "tx_transmit_q"
 public -module "ecap5_dwbuart" -var "tx_done"
 
-public -module "ecap5_dwbuart" -var "cr_clk_div_q"
+public -module "ecap5_dwbuart" -var "cr_acc_incr_q"
 public -module "ecap5_dwbuart" -var "cr_ds_q"
 public -module "ecap5_dwbuart" -var "cr_s_q"
 public -module "ecap5_dwbuart" -var "cr_p_q"
diff --git a/tests/benches/rx_frontend/tb_rx_frontend.cpp b/tests/benches/rx_frontend/tb_rx_frontend.cpp
index 49a974e..e59ddc9 100644
--- a/tests/benches/rx_frontend/tb_rx_frontend.cpp
+++ b/tests/benches/rx_frontend/tb_rx_frontend.cpp
@@ -83,7 +83,7 @@ class TB_Rx_frontend : public Testbench<Vtb_rx_frontend> {
   
   void _nop() {
     core->uart_rx_i = 1;
-    core->cr_clk_div_i = 0;
+    core->cr_acc_incr_i = 0;
     core->cr_ds_i = 0;
     core->cr_p_i = 0;
     core->cr_s_i = 0;
@@ -174,7 +174,7 @@ void tb_rx_frontend_valid_frame_7N1(TB_Rx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  core->cr_acc_incr_i = (65535/4);
   core->cr_ds_i = 0;
   core->cr_p_i = 0;
   core->cr_s_i = 0;
@@ -367,7 +367,7 @@ void tb_rx_frontend_valid_frame_7N2(TB_Rx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  core->cr_acc_incr_i = (65535/4);
   core->cr_ds_i = 0;
   core->cr_p_i = 0;
   core->cr_s_i = 1;
@@ -570,7 +570,7 @@ void tb_rx_frontend_valid_frame_7E1(TB_Rx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  core->cr_acc_incr_i = (65535/4);
   core->cr_ds_i = 0;
   core->cr_p_i = 2;
   core->cr_s_i = 0;
@@ -773,7 +773,7 @@ void tb_rx_frontend_valid_frame_7E2(TB_Rx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  core->cr_acc_incr_i = (65535/4);
   core->cr_ds_i = 0;
   core->cr_p_i = 2;
   core->cr_s_i = 1;
@@ -986,7 +986,7 @@ void tb_rx_frontend_valid_frame_7O1(TB_Rx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  core->cr_acc_incr_i = (65535/4);
   core->cr_ds_i = 0;
   core->cr_p_i = 1;
   core->cr_s_i = 0;
@@ -1189,7 +1189,7 @@ void tb_rx_frontend_valid_frame_7O2(TB_Rx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  core->cr_acc_incr_i = (65535/4);
   core->cr_ds_i = 0;
   core->cr_p_i = 1;
   core->cr_s_i = 1;
@@ -1402,7 +1402,7 @@ void tb_rx_frontend_valid_frame_8N1(TB_Rx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  core->cr_acc_incr_i = (65535/4);
   core->cr_ds_i = 1;
   core->cr_p_i = 0;
   core->cr_s_i = 0;
@@ -1605,7 +1605,7 @@ void tb_rx_frontend_valid_frame_8N2(TB_Rx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  core->cr_acc_incr_i = (65535/4);
   core->cr_ds_i = 1;
   core->cr_p_i = 0;
   core->cr_s_i = 1;
@@ -1818,7 +1818,7 @@ void tb_rx_frontend_valid_frame_8E1(TB_Rx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  core->cr_acc_incr_i = (65535/4);
   core->cr_ds_i = 1;
   core->cr_p_i = 2;
   core->cr_s_i = 0;
@@ -2031,7 +2031,7 @@ void tb_rx_frontend_valid_frame_8E2(TB_Rx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  core->cr_acc_incr_i = (65535/4);
   core->cr_ds_i = 1;
   core->cr_p_i = 2;
   core->cr_s_i = 1;
@@ -2254,7 +2254,7 @@ void tb_rx_frontend_valid_frame_8O1(TB_Rx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  core->cr_acc_incr_i = (65535/4);
   core->cr_ds_i = 1;
   core->cr_p_i = 1;
   core->cr_s_i = 0;
@@ -2467,7 +2467,7 @@ void tb_rx_frontend_valid_frame_8O2(TB_Rx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  core->cr_acc_incr_i = (65535/4);
   core->cr_ds_i = 1;
   core->cr_p_i = 1;
   core->cr_s_i = 1;
@@ -2690,7 +2690,7 @@ void tb_rx_frontend_baudrate(TB_Rx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 100;
+  core->cr_acc_incr_i = (65535/100);
   core->cr_ds_i = 0;
   core->cr_p_i = 0;
   core->cr_s_i = 0;
@@ -2902,7 +2902,7 @@ void tb_rx_frontend_parity_even(TB_Rx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  core->cr_acc_incr_i = (65535/4);
   core->cr_ds_i = 0;
   core->cr_p_i = 2;
   core->cr_s_i = 0;
@@ -3158,7 +3158,7 @@ void tb_rx_frontend_parity_odd(TB_Rx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  core->cr_acc_incr_i = (65535/4);
   core->cr_ds_i = 0;
   core->cr_p_i = 1;
   core->cr_s_i = 0;
diff --git a/tests/benches/rx_frontend/tb_rx_frontend.sv b/tests/benches/rx_frontend/tb_rx_frontend.sv
index b0ed507..69cc99f 100644
--- a/tests/benches/rx_frontend/tb_rx_frontend.sv
+++ b/tests/benches/rx_frontend/tb_rx_frontend.sv
@@ -27,7 +27,7 @@ module tb_rx_frontend
   input   logic         clk_i,
   input   logic         rst_i,
 
-  input   logic[15:0]   cr_clk_div_i,
+  input   logic[15:0]   cr_acc_incr_i,
   input   logic         cr_ds_i,
   input   logic[1:0]    cr_p_i,
   input   logic         cr_s_i,
@@ -44,7 +44,7 @@ rx_frontend dut (
   .clk_i           (clk_i),
   .rst_i           (rst_i),
                  
-  .cr_clk_div_i    (cr_clk_div_i),
+  .cr_acc_incr_i    (cr_acc_incr_i),
   .cr_ds_i         (cr_ds_i),
   .cr_p_i          (cr_p_i),
   .cr_s_i          (cr_s_i),
diff --git a/tests/benches/tx_frontend/tb_tx_frontend.cpp b/tests/benches/tx_frontend/tb_tx_frontend.cpp
index 25f5139..53457fb 100644
--- a/tests/benches/tx_frontend/tb_tx_frontend.cpp
+++ b/tests/benches/tx_frontend/tb_tx_frontend.cpp
@@ -36,6 +36,7 @@ enum CondId {
   COND_state,
   COND_output,
   COND_done,
+  COND_baudrate,
   __CondIdEnd
 };
 
@@ -79,7 +80,7 @@ class TB_Tx_frontend : public Testbench<Vtb_tx_frontend> {
   }
   
   void _nop() {
-    core->cr_clk_div_i = 0;
+    core->cr_acc_incr_i = 0;
     core->cr_ds_i = 0;
     core->cr_p_i = 0;
     core->cr_s_i = 0;
@@ -88,10 +89,37 @@ class TB_Tx_frontend : public Testbench<Vtb_tx_frontend> {
     core->dr_i = 0;
   }
 
-  void n_tick(int n) {
-    for(int i = 0; i < n; i++) {
+  float get_generated_baudrate(uint32_t baudrate) {
+    this->reset();
+
+    core->cr_acc_incr_i = ((double)baudrate * (1 << 16)) / 24000000;
+    core->cr_ds_i = 1;
+    core->cr_p_i = 1;
+    core->cr_s_i = 1;
+
+    core->transmit_i = 1;
+    core->dr_i = 0x7A;
+
+    // Wait for the tx signal to go down
+    while(core->uart_tx_o == 1) {
+      this->tick();
+    }
+
+    // Initializes the clock counter
+    uint32_t counter = 0;
+
+    // Wait for the end of the transfer
+    while(core->done_o != 1) {
+      counter += 1; 
+
       this->tick();
     }
+
+    // Compute the baudrate
+    float duration = (counter / 24000000.0);
+    float baud_period = duration / 12;
+    float generated_baudrate = (1.0 / baud_period);
+    return generated_baudrate;
   }
 };
 
@@ -181,7 +209,8 @@ void tb_tx_frontend_7N1(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  // Baudrate = 2500000 -> 9.6 cycles d'horloge
+  core->cr_acc_incr_i = 6827;
   core->cr_ds_i = 0;
   core->cr_p_i = 0;
   core->cr_s_i = 0;
@@ -207,111 +236,152 @@ void tb_tx_frontend_7N1(TB_Tx_frontend * tb) {
   core->transmit_i = 0;
 
   //=================================
-  //      Tick (2-5)
+  //      Tick (2-10)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (6-9)
+  //      Tick (11-20)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (10-13)
+  //      Tick (21-29)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (14-17)
+  //      Tick (30-39)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (18-21)
+  //      Tick (40-49)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (22-25)
+  //      Tick (50-58)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (59-68)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (26-29)
+  //      Tick (69-77)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (78-87)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (30-33)
+  //      Tick (88)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
+  tb->check(COND_done,   (core->done_o == 1));
 
   //=================================
-  //      Tick (34-37)
+  //      Tick (89)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
   tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_done,   (core->done_o == 1));
+  tb->check(COND_done,   (core->done_o == 0));
 
   //`````````````````````````````````
   //      Formal Checks 
@@ -341,7 +411,8 @@ void tb_tx_frontend_7N2(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  // Baudrate = 2500000 -> 9.6 cycles d'horloge
+  core->cr_acc_incr_i = 6827;
   core->cr_ds_i = 0;
   core->cr_p_i = 0;
   core->cr_s_i = 1;
@@ -367,123 +438,166 @@ void tb_tx_frontend_7N2(TB_Tx_frontend * tb) {
   core->transmit_i = 0;
 
   //=================================
-  //      Tick (2-5)
+  //      Tick (2-10)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (6-9)
+  //      Tick (11-20)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (10-13)
+  //      Tick (21-29)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (14-17)
+  //      Tick (30-39)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (18-21)
+  //      Tick (40-49)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (22-25)
+  //      Tick (50-58)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (26-29)
+  //      Tick (59-68)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (69-77)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (30-33)
+  //      Tick (78-87)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (88-96)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (34-37)
+  //      Tick (97)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
+  tb->check(COND_done,   (core->done_o == 1));
 
   //=================================
-  //      Tick (38-41)
+  //      Tick (98)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
   tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_done,   (core->done_o == 1));
+  tb->check(COND_done,   (core->done_o == 0));
 
   //`````````````````````````````````
   //      Formal Checks 
@@ -513,7 +627,8 @@ void tb_tx_frontend_7E1(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  // Baudrate = 2500000 -> 9.6 cycles d'horloge
+  core->cr_acc_incr_i = 6827;
   core->cr_ds_i = 0;
   core->cr_p_i = 2;
   core->cr_s_i = 0;
@@ -539,123 +654,167 @@ void tb_tx_frontend_7E1(TB_Tx_frontend * tb) {
   core->transmit_i = 0;
 
   //=================================
-  //      Tick (2-5)
+  //      Tick (2-10)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (6-9)
+  //      Tick (11-20)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (10-13)
+  //      Tick (21-29)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (14-17)
+  //      Tick (30-39)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (18-21)
+  //      Tick (40-49)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (22-25)
+  //      Tick (50-58)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (26-29)
+  //      Tick (59-68)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (69-77)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (30-33)
+  //      Tick (78-87)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_PARITY));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (88-96)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_PARITY));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (34-37)
+  //      Tick (97)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
+  tb->check(COND_done,   (core->done_o == 1));
 
   //=================================
-  //      Tick (38-41)
+  //      Tick (98)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
   tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_done,   (core->done_o == 1));
+  tb->check(COND_done,   (core->done_o == 0));
+
 
   //`````````````````````````````````
   //      Formal Checks 
@@ -671,11 +830,12 @@ void tb_tx_frontend_7E1(TB_Tx_frontend * tb) {
   CHECK("tb_tx_frontend.7E1.03",
       tb->conditions[COND_done],
       "Failed to implement the done signal", tb->err_cycles[COND_done]);
+  
 }
 
 void tb_tx_frontend_7E2(TB_Tx_frontend * tb) {
   Vtb_tx_frontend * core = tb->core;
-  core->testcase = T_7E1;
+  core->testcase = T_7E2;
 
   //=================================
   //      Tick (0)
@@ -685,13 +845,14 @@ void tb_tx_frontend_7E2(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  // Baudrate = 2500000 -> 9.6 cycles d'horloge
+  core->cr_acc_incr_i = 6827;
   core->cr_ds_i = 0;
   core->cr_p_i = 2;
-  core->cr_s_i = 0;
+  core->cr_s_i = 1;
 
   core->transmit_i = 1;
-  core->dr_i = 0x4A;
+  core->dr_i = 0x3A;
 
   //=================================
   //      Tick (1)
@@ -711,117 +872,163 @@ void tb_tx_frontend_7E2(TB_Tx_frontend * tb) {
   core->transmit_i = 0;
 
   //=================================
-  //      Tick (2-5)
+  //      Tick (2-10)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (6-9)
+  //      Tick (11-20)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (10-13)
+  //      Tick (21-29)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (14-17)
+  //      Tick (30-39)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (18-21)
+  //      Tick (40-49)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (22-25)
+  //      Tick (50-58)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (26-29)
+  //      Tick (59-68)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (30-33)
+  //      Tick (69-77)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (78-87)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_PARITY));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_PARITY));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (34-37)
+  //      Tick (88-96)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (97-106)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (38-41)
+  //      Tick (107)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Checks 
@@ -829,6 +1036,17 @@ void tb_tx_frontend_7E2(TB_Tx_frontend * tb) {
   tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
   tb->check(COND_done,   (core->done_o == 1));
 
+  //=================================
+  //      Tick (108)
+  
+  tb->tick();
+
+  //`````````````````````````````````
+  //      Checks 
+  
+  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
+  tb->check(COND_done,   (core->done_o == 0));
+
   //`````````````````````````````````
   //      Formal Checks 
   
@@ -857,13 +1075,14 @@ void tb_tx_frontend_7O1(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  // Baudrate = 2500000 -> 9.6 cycles d'horloge
+  core->cr_acc_incr_i = 6827;
   core->cr_ds_i = 0;
   core->cr_p_i = 1;
   core->cr_s_i = 0;
 
   core->transmit_i = 1;
-  core->dr_i = 0x7A;
+  core->dr_i = 0x3A;
 
   //=================================
   //      Tick (1)
@@ -883,123 +1102,166 @@ void tb_tx_frontend_7O1(TB_Tx_frontend * tb) {
   core->transmit_i = 0;
 
   //=================================
-  //      Tick (2-5)
+  //      Tick (2-10)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (6-9)
+  //      Tick (11-20)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (10-13)
+  //      Tick (21-29)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (14-17)
+  //      Tick (30-39)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (18-21)
+  //      Tick (40-49)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (22-25)
+  //      Tick (50-58)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (26-29)
+  //      Tick (59-68)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (69-77)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (30-33)
+  //      Tick (78-87)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_PARITY));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (88-96)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_PARITY));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (34-37)
+  //      Tick (97)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
+  tb->check(COND_done,   (core->done_o == 1));
 
   //=================================
-  //      Tick (38-41)
+  //      Tick (98)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
   tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_done,   (core->done_o == 1));
+  tb->check(COND_done,   (core->done_o == 0));
 
   //`````````````````````````````````
   //      Formal Checks 
@@ -1029,13 +1291,14 @@ void tb_tx_frontend_7O2(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  // Baudrate = 2500000 -> 9.6 cycles d'horloge
+  core->cr_acc_incr_i = 6827;
   core->cr_ds_i = 0;
   core->cr_p_i = 1;
-  core->cr_s_i = 0;
+  core->cr_s_i = 1;
 
   core->transmit_i = 1;
-  core->dr_i = 0x4A;
+  core->dr_i = 0x3A;
 
   //=================================
   //      Tick (1)
@@ -1055,123 +1318,180 @@ void tb_tx_frontend_7O2(TB_Tx_frontend * tb) {
   core->transmit_i = 0;
 
   //=================================
-  //      Tick (2-5)
+  //      Tick (2-10)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (6-9)
+  //      Tick (11-20)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (10-13)
+  //      Tick (21-29)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (14-17)
+  //      Tick (30-39)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (18-21)
+  //      Tick (40-49)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (22-25)
+  //      Tick (50-58)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (59-68)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (26-29)
+  //      Tick (69-77)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (78-87)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_PARITY));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (30-33)
+  //      Tick (88-96)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (97-106)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_PARITY));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (34-37)
+  //      Tick (107)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
+  tb->check(COND_done,   (core->done_o == 1));
 
   //=================================
-  //      Tick (38-41)
+  //      Tick (108)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
   tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_done,   (core->done_o == 1));
+  tb->check(COND_done,   (core->done_o == 0));
 
   //`````````````````````````````````
   //      Formal Checks 
@@ -1201,7 +1521,8 @@ void tb_tx_frontend_8N1(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  // Baudrate = 2500000 -> 9.6 cycles d'horloge
+  core->cr_acc_incr_i = 6827;
   core->cr_ds_i = 1;
   core->cr_p_i = 0;
   core->cr_s_i = 0;
@@ -1227,123 +1548,166 @@ void tb_tx_frontend_8N1(TB_Tx_frontend * tb) {
   core->transmit_i = 0;
 
   //=================================
-  //      Tick (2-5)
+  //      Tick (2-10)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (6-9)
+  //      Tick (11-20)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (10-13)
+  //      Tick (21-29)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (14-17)
+  //      Tick (30-39)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (18-21)
+  //      Tick (40-49)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (22-25)
+  //      Tick (50-58)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (26-29)
+  //      Tick (59-68)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (69-77)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (30-33)
+  //      Tick (78-87)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (88-96)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (34-37)
+  //      Tick (97)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
+  tb->check(COND_done,   (core->done_o == 1));
 
   //=================================
-  //      Tick (38-41)
+  //      Tick (98)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
   tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_done,   (core->done_o == 1));
+  tb->check(COND_done,   (core->done_o == 0));
 
   //`````````````````````````````````
   //      Formal Checks 
@@ -1373,7 +1737,8 @@ void tb_tx_frontend_8N2(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  // Baudrate = 2500000 -> 9.6 cycles d'horloge
+  core->cr_acc_incr_i = 6827;
   core->cr_ds_i = 1;
   core->cr_p_i = 0;
   core->cr_s_i = 1;
@@ -1399,135 +1764,180 @@ void tb_tx_frontend_8N2(TB_Tx_frontend * tb) {
   core->transmit_i = 0;
 
   //=================================
-  //      Tick (2-5)
+  //      Tick (2-10)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (6-9)
+  //      Tick (11-20)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (10-13)
+  //      Tick (21-29)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (14-17)
+  //      Tick (30-39)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (18-21)
+  //      Tick (40-49)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (22-25)
+  //      Tick (50-58)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (26-29)
+  //      Tick (59-68)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (30-33)
+  //      Tick (69-77)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (78-87)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (34-37)
+  //      Tick (88-96)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (97-106)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (38-41)
+  //      Tick (107)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
+  tb->check(COND_done,   (core->done_o == 1));
 
   //=================================
-  //      Tick (42-45)
+  //      Tick (108)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
   tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_done,   (core->done_o == 1));
+  tb->check(COND_done,   (core->done_o == 0));
 
   //`````````````````````````````````
   //      Formal Checks 
@@ -1557,7 +1967,8 @@ void tb_tx_frontend_8E1(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  // Baudrate = 2500000 -> 9.6 cycles d'horloge
+  core->cr_acc_incr_i = 6827;
   core->cr_ds_i = 1;
   core->cr_p_i = 2;
   core->cr_s_i = 0;
@@ -1583,135 +1994,181 @@ void tb_tx_frontend_8E1(TB_Tx_frontend * tb) {
   core->transmit_i = 0;
 
   //=================================
-  //      Tick (2-5)
+  //      Tick (2-10)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (6-9)
+  //      Tick (11-20)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (10-13)
+  //      Tick (21-29)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (14-17)
+  //      Tick (30-39)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (18-21)
+  //      Tick (40-49)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (22-25)
+  //      Tick (50-58)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (26-29)
+  //      Tick (59-68)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (30-33)
+  //      Tick (69-77)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (78-87)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (34-37)
+  //      Tick (88-96)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_PARITY));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (97-106)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_PARITY));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (38-41)
+  //      Tick (107)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
+  tb->check(COND_done,   (core->done_o == 1));
 
   //=================================
-  //      Tick (42-45)
+  //      Tick (108)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
   tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_done,   (core->done_o == 1));
+  tb->check(COND_done,   (core->done_o == 0));
+
 
   //`````````````````````````````````
   //      Formal Checks 
@@ -1741,13 +2198,14 @@ void tb_tx_frontend_8E2(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  // Baudrate = 2500000 -> 9.6 cycles d'horloge
+  core->cr_acc_incr_i = 6827;
   core->cr_ds_i = 1;
   core->cr_p_i = 2;
   core->cr_s_i = 1;
 
   core->transmit_i = 1;
-  core->dr_i = 0x3A;
+  core->dr_i = 0x7A;
 
   //=================================
   //      Tick (1)
@@ -1767,147 +2225,194 @@ void tb_tx_frontend_8E2(TB_Tx_frontend * tb) {
   core->transmit_i = 0;
 
   //=================================
-  //      Tick (2-5)
+  //      Tick (2-10)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (6-9)
+  //      Tick (11-20)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (10-13)
+  //      Tick (21-29)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (14-17)
+  //      Tick (30-39)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (18-21)
+  //      Tick (40-49)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (22-25)
+  //      Tick (50-58)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (26-29)
+  //      Tick (59-68)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (30-33)
+  //      Tick (69-77)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (34-37)
+  //      Tick (78-87)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (88-96)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_PARITY));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_PARITY));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (38-41)
+  //      Tick (97-106)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (107-116)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (42-45)
+  //      Tick (117)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
+  tb->check(COND_done,   (core->done_o == 1));
 
   //=================================
-  //      Tick (46-49)
+  //      Tick (118)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
   tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_done,   (core->done_o == 1));
+  tb->check(COND_done,   (core->done_o == 0));
 
   //`````````````````````````````````
   //      Formal Checks 
@@ -1937,7 +2442,8 @@ void tb_tx_frontend_8O1(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  // Baudrate = 2500000 -> 9.6 cycles d'horloge
+  core->cr_acc_incr_i = 6827;
   core->cr_ds_i = 1;
   core->cr_p_i = 1;
   core->cr_s_i = 0;
@@ -1963,135 +2469,180 @@ void tb_tx_frontend_8O1(TB_Tx_frontend * tb) {
   core->transmit_i = 0;
 
   //=================================
-  //      Tick (2-5)
+  //      Tick (2-10)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (6-9)
+  //      Tick (11-20)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (10-13)
+  //      Tick (21-29)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (14-17)
+  //      Tick (30-39)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (18-21)
+  //      Tick (40-49)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (22-25)
+  //      Tick (50-58)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (26-29)
+  //      Tick (59-68)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (30-33)
+  //      Tick (69-77)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (78-87)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (34-37)
+  //      Tick (88-96)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_PARITY));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (97-106)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_PARITY));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (38-41)
+  //      Tick (107)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
+  tb->check(COND_done,   (core->done_o == 1));
 
   //=================================
-  //      Tick (42-45)
+  //      Tick (108)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
   tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_done,   (core->done_o == 1));
+  tb->check(COND_done,   (core->done_o == 0));
 
   //`````````````````````````````````
   //      Formal Checks 
@@ -2121,13 +2672,14 @@ void tb_tx_frontend_8O2(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->cr_clk_div_i = 4;
+  // Baudrate = 2500000 -> 9.6 cycles d'horloge
+  core->cr_acc_incr_i = 6827;
   core->cr_ds_i = 1;
   core->cr_p_i = 1;
   core->cr_s_i = 1;
 
   core->transmit_i = 1;
-  core->dr_i = 0x3A;
+  core->dr_i = 0x7A;
 
   //=================================
   //      Tick (1)
@@ -2147,147 +2699,194 @@ void tb_tx_frontend_8O2(TB_Tx_frontend * tb) {
   core->transmit_i = 0;
 
   //=================================
-  //      Tick (2-5)
+  //      Tick (2-10)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (6-9)
+  //      Tick (11-20)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (10-13)
+  //      Tick (21-29)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (14-17)
+  //      Tick (30-39)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (18-21)
+  //      Tick (40-49)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (22-25)
+  //      Tick (50-58)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (26-29)
+  //      Tick (59-68)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (30-33)
+  //      Tick (69-77)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (34-37)
+  //      Tick (78-87)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (88-96)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_PARITY));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 9; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_PARITY));
+    tb->check(COND_output, (core->uart_tx_o == 0));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (38-41)
+  //      Tick (97-106)
   
-  tb->n_tick(4);
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
+
+  //=================================
+  //      Tick (107-116)
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+  for(size_t i = 0; i < 10; i++) {
+    tb->tick();
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
+    tb->check(COND_output, (core->uart_tx_o == 1));
+    tb->check(COND_done,   (core->done_o == 0));
+  }
 
   //=================================
-  //      Tick (42-45)
+  //      Tick (117)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
+  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
+  tb->check(COND_done,   (core->done_o == 1));
 
   //=================================
-  //      Tick (46-49)
+  //      Tick (118)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
   tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_done,   (core->done_o == 1));
+  tb->check(COND_done,   (core->done_o == 0));
 
   //`````````````````````````````````
   //      Formal Checks 
@@ -2309,160 +2908,38 @@ void tb_tx_frontend_baudrate(TB_Tx_frontend * tb) {
   Vtb_tx_frontend * core = tb->core;
   core->testcase = T_BAUDRATE;
 
-  //=================================
-  //      Tick (0)
-  
-  tb->reset();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->cr_clk_div_i = 100;
-  core->cr_ds_i = 0;
-  core->cr_p_i = 0;
-  core->cr_s_i = 0;
-
-  core->transmit_i = 1;
-  core->dr_i = 0x3A;
-
-  //=================================
-  //      Tick (1)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->transmit_i = 0;
-
-  //=================================
-  //      Tick (2-5)
-  
-  tb->n_tick(100);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
-
-  //=================================
-  //      Tick (6-9)
-  
-  tb->n_tick(100);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
-
-  //=================================
-  //      Tick (10-13)
-  
-  tb->n_tick(100);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
-
-  //=================================
-  //      Tick (14-17)
-  
-  tb->n_tick(100);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
-
-  //=================================
-  //      Tick (18-21)
-  
-  tb->n_tick(100);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
-
-  //=================================
-  //      Tick (22-25)
-  
-  tb->n_tick(100);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
-
-  //=================================
-  //      Tick (26-29)
-  
-  tb->n_tick(100);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_output, (core->uart_tx_o == 0));
-  tb->check(COND_done,   (core->done_o == 0));
-
-  //=================================
-  //      Tick (30-33)
-  
-  tb->n_tick(100);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
-  tb->check(COND_output, (core->uart_tx_o == 1));
-  tb->check(COND_done,   (core->done_o == 0));
-
-  //=================================
-  //      Tick (34-37)
-  
-  tb->n_tick(100);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_done,   (core->done_o == 1));
+  uint32_t baudrates[] = {
+    4800,
+    9600,
+    19200,
+    38400,
+    57600,
+    115200,
+    230400,
+    460800,
+    921600,
+    1000000,
+    2000000,
+    3000000
+  };
+  size_t num_baudrates = sizeof(baudrates)/sizeof(uint32_t);
+
+  for(size_t i = 0; i < num_baudrates; i++) {
+    float generated_baudrate = tb->get_generated_baudrate(baudrates[i]);
+    float precision = (1.0 - (generated_baudrate / baudrates[i]));
+
+    //`````````````````````````````````
+    //      Checks 
+    
+    tb->check(COND_baudrate,  (precision < 0.02));
+  }
 
   //`````````````````````````````````
   //      Formal Checks 
   
   CHECK("tb_tx_frontend.baudrate.01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
-
-  CHECK("tb_tx_frontend.baudrate.02",
-      tb->conditions[COND_output],
-      "Failed to implement the output signal", tb->err_cycles[COND_output]);
-
-  CHECK("tb_tx_frontend.baudrate.03",
-      tb->conditions[COND_done],
-      "Failed to implement the done signal", tb->err_cycles[COND_done]);
+      tb->conditions[COND_baudrate],
+      "Failed to comply with the baudrate precision", tb->err_cycles[COND_baudrate]);
 }
 
 int main(int argc, char ** argv, char ** env) {
@@ -2470,6 +2947,7 @@ int main(int argc, char ** argv, char ** env) {
   Verilated::traceEverOn(true);
 
   bool verbose = parse_verbose(argc, argv);
+  verbose = true;
 
   TB_Tx_frontend * tb = new TB_Tx_frontend;
   tb->open_trace("waves/tx_frontend.vcd");
@@ -2477,6 +2955,9 @@ int main(int argc, char ** argv, char ** env) {
   tb->set_debug_log(verbose);
   tb->init_conditions(__CondIdEnd);
 
+  // 24MHz
+  tb->clk_period_in_ps = 41667;
+
   /************************************************************/
 
   tb_tx_frontend_idle(tb);
diff --git a/tests/benches/tx_frontend/tb_tx_frontend.sv b/tests/benches/tx_frontend/tb_tx_frontend.sv
index fb9b874..f2cad03 100644
--- a/tests/benches/tx_frontend/tb_tx_frontend.sv
+++ b/tests/benches/tx_frontend/tb_tx_frontend.sv
@@ -27,7 +27,7 @@ module tb_tx_frontend
   input   logic         clk_i,
   input   logic         rst_i,
 
-  input   logic[15:0]   cr_clk_div_i,
+  input   logic[15:0]   cr_acc_incr_i,
   input   logic         cr_ds_i,
   input   logic[1:0]    cr_p_i,
   input   logic         cr_s_i,
@@ -44,7 +44,7 @@ tx_frontend dut (
   .clk_i           (clk_i),
   .rst_i           (rst_i),
                  
-  .cr_clk_div_i    (cr_clk_div_i),
+  .cr_acc_incr_i   (cr_acc_incr_i),
   .cr_ds_i         (cr_ds_i),
   .cr_p_i          (cr_p_i),
   .cr_s_i          (cr_s_i),

From c5acd35fff3af79b1abb642ab6223c1c40ac553a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Cl=C3=A9ment=20Chaine?= <clement.chaine25@gmail.com>
Date: Sat, 29 Nov 2025 19:37:02 +0100
Subject: [PATCH 05/15] Fix wrong CR value when reading

---
 src/ecap5_dwbuart.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/ecap5_dwbuart.sv b/src/ecap5_dwbuart.sv
index 8b275a7..726fdfd 100644
--- a/src/ecap5_dwbuart.sv
+++ b/src/ecap5_dwbuart.sv
@@ -171,7 +171,7 @@ always_comb begin : register_access
   mem_read_data_d = 0;
   case(mem_addr[7:2])
     UART_SR:   mem_read_data_d = {27'b0, sr_pe_q, sr_fe_q, sr_rxoe_q, sr_txe_q, sr_rxne_q};
-    UART_CR:   mem_read_data_d = {cr_acc_incr_q, 12'b0, cr_s_q, cr_p_q, cr_ds_q};
+    UART_CR:   mem_read_data_d = {cr_acc_incr_q, 12'b0, cr_ds_q, cr_s_q, cr_p_q};
     UART_RXDR: mem_read_data_d = {24'b0, rxdr_rxd_q};
     default:   mem_read_data_d = '0;
   endcase

From 2d828172e02c9ed9044d0eb15ce24ce75d44aa68 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Cl=C3=A9ment=20Chaine?= <clement.chaine25@gmail.com>
Date: Sun, 30 Nov 2025 23:07:23 +0100
Subject: [PATCH 06/15] Fix testbenches with support for arbitrary baud rates

---
 src/rx_frontend.sv                           |   58 +-
 tests/benches/rx_frontend/tb_rx_frontend.cpp | 3759 +++---------------
 tests/benches/rx_frontend/tb_rx_frontend.sv  |    3 +-
 tests/benches/tx_frontend/tb_tx_frontend.cpp |    1 -
 4 files changed, 593 insertions(+), 3228 deletions(-)

diff --git a/src/rx_frontend.sv b/src/rx_frontend.sv
index 9c1da01..a0d0b19 100644
--- a/src/rx_frontend.sv
+++ b/src/rx_frontend.sv
@@ -53,8 +53,8 @@ state_t state_d, state_q;
 
 logic uart_rx_q, uart_rx_qq, uart_rx_qqq;
 
-logic[15:0] half_baud_cnt_d, half_baud_cnt_q, 
-                 baud_cnt_d,      baud_cnt_q;
+logic[16:0] baud_acc_d, baud_acc_q;
+logic baud_acc_half_overflow, baud_acc_overflow;;
 
 logic[MAX_FRAME_SIZE:0]  frame_bit_cnt_d, frame_bit_cnt_q;
 
@@ -82,13 +82,13 @@ always_comb begin : state_machine
   case(state_q)
     IDLE: begin
       // Wait for the beginning of the start bit
-      if(uart_rx_qqq == 0) begin
+      if(uart_rx_qq == 0) begin
         state_d = START;
       end
     end
     START: begin
       // Wait for the middle of the start bit
-      if(half_baud_cnt_q == '0) begin
+      if(baud_acc_half_overflow) begin
         state_d = DATA;
       end
     end
@@ -103,8 +103,7 @@ always_comb begin : state_machine
 end
 
 always_comb begin : sampling
-  half_baud_cnt_d = 0;
-  baud_cnt_d = 0;
+  baud_acc_d = 0;
   frame_bit_cnt_d = frame_bit_cnt_q;
   frame_d = frame_q;
   parity_d = parity_q;
@@ -120,23 +119,27 @@ always_comb begin : sampling
 
   parity_bit = cr_ds_i ? frame_shifted[8] : frame_shifted[7];
 
+  // Baudrate accumulator overflow
+  baud_acc_overflow = baud_acc_q[16];
+  baud_acc_half_overflow = baud_acc_q[15];
+
   case(state_q)
     IDLE: begin
-      // We initialize the half_baud_rate counter at the start of the start bit
-      if(uart_rx_qqq == 0) begin
-        // It takes one cycle for this counter to be decremented (switch to START state)
-        // It takes on cycle for logic to detect this counter is null
-        // The counter is therefore initialized to half the baud interval - 2
-        half_baud_cnt_d = {1'b0, cr_acc_incr_i[15:1]} - 2;
+      // We initialize the baud_rate counter at the start of the start bit
+      if(uart_rx_qq == 0) begin
+        // This is initialized to (2**15) as we want it to overflow in half the baud period
+        // so that we sample in the middle of the bits
+        baud_acc_d = {2'b0, cr_acc_incr_i[14:0]};
       end
     end
     START: begin
-      half_baud_cnt_d = half_baud_cnt_q - 1;
+      baud_acc_d = {2'b0, baud_acc_q[14:0]} + {2'b0, cr_acc_incr_i[14:0]};
       // We initialize the data counter when reaching the middle of the start bit
-      if(half_baud_cnt_q == '0) begin
+      // This is reached when the 15th bit is set.
+      if(baud_acc_half_overflow) begin
         // It takes one cycle for logic to detect this counter is null
-        // The counter is therefore initialized to the baud interval - 1
-        baud_cnt_d = cr_acc_incr_i - 1;
+        // The counter is therefore initialized to acc_incr (1 cycle)
+        baud_acc_d = {1'b0, cr_acc_incr_i[15:0]};
         // Initialize the frame size ring counter
         frame_bit_cnt_d[0] = 1'b1;
         // Initialize the parity bit with the parity configuration bit
@@ -145,19 +148,17 @@ always_comb begin : sampling
       end
     end
     DATA: begin
-      if(baud_cnt_q == '0) begin
+      if(baud_acc_overflow) begin
         // When the baud interval has elapsed
-        //   1. reset the baud counter
-        //   2. decrement the frame bit counter
-        //   3. sample the input
-        //   4. update the computed parity
-        baud_cnt_d = cr_acc_incr_i - 1;
+        //   1. decrement the frame bit counter
+        //   1. sample the input
+        //   1. update the computed parity
         frame_bit_cnt_d = {frame_bit_cnt_d[MAX_FRAME_SIZE-1:0], 1'b0};
         frame_d = {uart_rx_qqq, frame_q[10:1]};
         parity_d = parity_q ^ (uart_rx_qqq & (~data_bit_cnt_done_q));
-      end else begin
-        baud_cnt_d = baud_cnt_q - 1;
       end
+      baud_acc_d = {1'b0, baud_acc_q[15:0]} + cr_acc_incr_i;
+
       // Reset the counter as it will not be incremented further
       if(frame_bit_cnt_done) begin
         frame_bit_cnt_d = '0;
@@ -182,8 +183,7 @@ always_ff @(posedge clk_i) begin
     uart_rx_qq      <= 1;
     uart_rx_qqq     <= 1;
 
-    half_baud_cnt_q     <= '0;
-    baud_cnt_q          <= '0;
+    baud_acc_q          <= '0;
     frame_q             <= '0;
     frame_bit_cnt_q     <= '0;
     data_bit_cnt_done_q <=  0;
@@ -197,12 +197,8 @@ always_ff @(posedge clk_i) begin
     uart_rx_qq  <= uart_rx_q;
     uart_rx_qqq <= uart_rx_qq;
 
-    // half baudrate counter used at the start of a frame to
-    // sample the serial signal in the middle of a bit
-    half_baud_cnt_q <= half_baud_cnt_d;
-
     // baudrate counter used to sample the serial signal
-    baud_cnt_q <= baud_cnt_d;
+    baud_acc_q <= baud_acc_d;
 
     // The frame shift register
     frame_q <= frame_d;
diff --git a/tests/benches/rx_frontend/tb_rx_frontend.cpp b/tests/benches/rx_frontend/tb_rx_frontend.cpp
index e59ddc9..d706255 100644
--- a/tests/benches/rx_frontend/tb_rx_frontend.cpp
+++ b/tests/benches/rx_frontend/tb_rx_frontend.cpp
@@ -67,8 +67,21 @@ enum StateId {
   S_STOP
 };
 
+typedef struct {
+  uint32_t baudrate;
+  uint32_t data;
+  uint8_t ds;
+  uint8_t p;
+  uint8_t s;
+  uint8_t inject_frame_error;
+  uint8_t inject_parity_error;
+} test_configuration_t;
+
 class TB_Rx_frontend : public Testbench<Vtb_rx_frontend> {
 public:
+  uint32_t accumulator_increment;
+  uint32_t accumulator;
+
   void reset() {
     this->_nop();
 
@@ -87,11 +100,114 @@ class TB_Rx_frontend : public Testbench<Vtb_rx_frontend> {
     core->cr_ds_i = 0;
     core->cr_p_i = 0;
     core->cr_s_i = 0;
+
+    core->test = 0;
+  }
+  
+  void set_injected_baudrate(uint32_t acc_increment) {
+    this->accumulator_increment = acc_increment;
+    this->accumulator = 0;
+  }
+
+  uint32_t get_cycles_before_next_accumulator_overflow() {
+    uint32_t cycles = 0;
+    while(this->accumulator < (1 << 16)) {
+      cycles += 1;
+      this->accumulator += this->accumulator_increment;
+    }
+
+    this->accumulator = this->accumulator & ((1 << 16) - 1);
+
+    return cycles;
   }
 
-  void n_tick(int n) {
-    for(int i = 0; i < n; i++) {
+  void test_with_injected_frame(test_configuration_t config) {
+    this->core->cr_acc_incr_i = ((double)config.baudrate * (1 << 16)) / 24000000;
+    this->core->cr_ds_i = config.ds;
+    this->core->cr_p_i = config.p;
+    this->core->cr_s_i = config.s;
+
+    this->tick();
+
+    set_injected_baudrate(this->core->cr_acc_incr_i);
+
+    // Send start bit
+    this->core->uart_rx_i = 0;
+
+    uint32_t cycles_to_run = get_cycles_before_next_accumulator_overflow();
+    uint32_t sampling_offset = 0;
+    for(int i = 0; i < cycles_to_run; i++) {
       this->tick();
+
+      // Count the number of cycles before sampling the first bit
+      if(core->tb_rx_frontend->dut->state_q == S_START) {
+        sampling_offset += 1;
+      }
+    }
+    
+    // Send data bits
+    uint32_t num_data_bits = config.ds ? 8 : 7;
+    for(int i = 0; i < num_data_bits; i++) {
+      this->core->uart_rx_i = (config.data >> i) & 1;
+
+      cycles_to_run = get_cycles_before_next_accumulator_overflow();
+      this->n_tick(cycles_to_run);
+    }
+
+    // Send parity bit
+    uint32_t num_parity_bits = config.p ? 1 : 0;
+    uint8_t parity = (config.p == 2) ? 0 : 1;
+    if(config.p) {
+      // Compute parity, starting with either 1 or 0 depending on ODD or EVEN
+      for(int j = 0; j < num_data_bits; j++) {
+        parity ^= (config.data >> j) & 1;
+      }
+
+      this->core->uart_rx_i = parity & 1;
+
+      // Inject a parity error
+      this->core->uart_rx_i ^= config.inject_parity_error; 
+
+      cycles_to_run = get_cycles_before_next_accumulator_overflow();
+      this->n_tick(cycles_to_run);
+    }
+
+    // Send stop bits
+    uint32_t num_stop_bits = config.s ? 2 : 1;
+
+    this->core->uart_rx_i = 1;
+    
+    // Inject a frame error
+    this->core->uart_rx_i ^= config.inject_frame_error;
+
+    for(int i = 0; i < num_stop_bits; i++) {
+      // If this is the last stop bit
+      if(i == (num_stop_bits - 1)) {
+        this->core->test = 1;
+        // Send half of the first cycle + 3 as the used signal is delayed by three
+        // clock cycles. Ceil is as sometimes cycles to run is not equal to the first
+        // cycle which created the sampling offset.
+        // This is done in order to catch the tx_done signal
+        cycles_to_run = get_cycles_before_next_accumulator_overflow();
+        this->n_tick(sampling_offset + 3);
+        this->core->test = 0;
+
+        // Check the result
+        uint32_t stop_bits = config.s ? 3 : 1;
+        uint32_t parity_bit = config.p ? parity : 0;
+        uint32_t data_bits = config.data & ((1 << num_data_bits) - 1);
+        uint32_t expected_frame = (stop_bits << (num_parity_bits + num_data_bits)) | (parity_bit << num_data_bits) | data_bits;
+        this->check(COND_frame,  (core->frame_o == expected_frame));
+        this->check(COND_errors, (core->parity_err_o == config.inject_parity_error) &&
+                                 (core->frame_err_o == config.inject_frame_error));
+        this->check(COND_valid, (core->output_valid_o == 1));
+
+        // Send the remaining of the first stop bit
+        this->n_tick(cycles_to_run - sampling_offset - 3);
+      } else {
+        cycles_to_run = get_cycles_before_next_accumulator_overflow();
+        this->n_tick(cycles_to_run);
+      }
     }
   }
 };
@@ -172,192 +288,257 @@ void tb_rx_frontend_valid_frame_7N1(TB_Rx_frontend * tb) {
   tb->reset();
 
   //`````````````````````````````````
-  //      Set inputs
-  
-  core->cr_acc_incr_i = (65535/4);
-  core->cr_ds_i = 0;
-  core->cr_p_i = 0;
-  core->cr_s_i = 0;
-
-  //=================================
-  //      Tick (1)
+  //      Checks 
   
-  tb->tick();
+  test_configuration_t config = {
+    .baudrate = 25000000,
+    .data = 0b10100101,
+    .ds = 0,
+    .p = 0,
+    .s = 0,
+    .inject_frame_error = 0,
+    .inject_parity_error = 0
+  };
+  tb->test_with_injected_frame(config);
 
   //`````````````````````````````````
-  //      Set inputs
+  //      Formal Checks 
   
-  core->uart_rx_i = 0;
+  CHECK("tb_rx_frontend.valid.7N1_01",
+      tb->conditions[COND_state],
+      "Failed to implement the state machine", tb->err_cycles[COND_state]);
 
-  //=================================
-  //      Tick (2-3)
-  
-  tb->n_tick(2);
+  CHECK("tb_rx_frontend.valid.7N1_02",
+      tb->conditions[COND_frame],
+      "Failed to implement the frame output", tb->err_cycles[COND_frame]);
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_valid, (core->output_valid_o == 0));
+  CHECK("tb_rx_frontend.valid.7N1_03",
+      tb->conditions[COND_errors],
+      "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
+
+  CHECK("tb_rx_frontend.valid.7N1_04",
+      tb->conditions[COND_valid],
+      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
+}
+
+void tb_rx_frontend_valid_frame_7N2(TB_Rx_frontend * tb) {
+  Vtb_rx_frontend * core = tb->core;
+  core->testcase = T_VALID_7N2;
 
   //=================================
-  //      Tick (4-5)
+  //      Tick (0)
   
-  tb->n_tick(2);
+  tb->reset();
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_START));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
+  test_configuration_t config = {
+    .baudrate = 25000000,
+    .data = 0b10100101,
+    .ds = 0,
+    .p = 0,
+    .s = 1,
+    .inject_frame_error = 0,
+    .inject_parity_error = 0
+  };
+  tb->test_with_injected_frame(config);
+  
   //`````````````````````````````````
-  //      Set inputs
+  //      Formal Checks 
   
-  core->uart_rx_i = 1;
+  CHECK("tb_rx_frontend.valid.7N2_01",
+      tb->conditions[COND_state],
+      "Failed to implement the state machine", tb->err_cycles[COND_state]);
+
+  CHECK("tb_rx_frontend.valid.7N2_02",
+      tb->conditions[COND_frame],
+      "Failed to implement the frame output", tb->err_cycles[COND_frame]);
+
+  CHECK("tb_rx_frontend.valid.7N2_03",
+      tb->conditions[COND_errors],
+      "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
+
+  CHECK("tb_rx_frontend.valid.7N2_04",
+      tb->conditions[COND_valid],
+      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
+}
+
+void tb_rx_frontend_valid_frame_7E1(TB_Rx_frontend * tb) {
+  Vtb_rx_frontend * core = tb->core;
+  core->testcase = T_VALID_7E1;
 
   //=================================
-  //      Tick (6-7)
+  //      Tick (0)
   
-  tb->n_tick(2);
+  tb->reset();
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (8-9)
-  
-  tb->n_tick(2);
+  test_configuration_t config = {
+    .baudrate = 25000000,
+    .data = 0b10100101,
+    .ds = 0,
+    .p = 2,
+    .s = 0,
+    .inject_frame_error = 0,
+    .inject_parity_error = 0
+  };
+  tb->test_with_injected_frame(config);
 
   //`````````````````````````````````
-  //      Set inputs
+  //      Formal Checks 
   
-  core->uart_rx_i = 0;
+  CHECK("tb_rx_frontend.valid.7E1_01",
+      tb->conditions[COND_state],
+      "Failed to implement the state machine", tb->err_cycles[COND_state]);
 
-  //=================================
-  //      Tick (10-13)
-  
-  tb->n_tick(4);
+  CHECK("tb_rx_frontend.valid.7E1_02",
+      tb->conditions[COND_frame],
+      "Failed to implement the frame output", tb->err_cycles[COND_frame]);
 
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
+  CHECK("tb_rx_frontend.valid.7E1_03",
+      tb->conditions[COND_errors],
+      "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
 
-  //=================================
-  //      Tick (14-17)
-  
-  tb->n_tick(4);
+  CHECK("tb_rx_frontend.valid.7E1_04",
+      tb->conditions[COND_valid],
+      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
+}
 
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
+void tb_rx_frontend_valid_frame_7E2(TB_Rx_frontend * tb) {
+  Vtb_rx_frontend * core = tb->core;
+  core->testcase = T_VALID_7E2;
 
   //=================================
-  //      Tick (18-21)
+  //      Tick (0)
   
-  tb->n_tick(4);
+  tb->reset();
 
   //`````````````````````````````````
-  //      Set inputs
+  //      Checks 
   
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (22-25)
+  test_configuration_t config = {
+    .baudrate = 25000000,
+    .data = 0b10100101,
+    .ds = 0,
+    .p = 2,
+    .s = 1,
+    .inject_frame_error = 0,
+    .inject_parity_error = 0
+  };
+  tb->test_with_injected_frame(config);
   
-  tb->n_tick(4);
-
   //`````````````````````````````````
-  //      Set inputs
+  //      Formal Checks 
   
-  core->uart_rx_i = 1;
+  CHECK("tb_rx_frontend.valid.7E2_01",
+      tb->conditions[COND_state],
+      "Failed to implement the state machine", tb->err_cycles[COND_state]);
 
-  //=================================
-  //      Tick (26-29)
-  
-  tb->n_tick(4);
+  CHECK("tb_rx_frontend.valid.7E2_02",
+      tb->conditions[COND_frame],
+      "Failed to implement the frame output", tb->err_cycles[COND_frame]);
 
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
+  CHECK("tb_rx_frontend.valid.7E2_03",
+      tb->conditions[COND_errors],
+      "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
 
-  //=================================
-  //      Tick (30-33)
-  
-  tb->n_tick(4);
+  CHECK("tb_rx_frontend.valid.7E2_04",
+      tb->conditions[COND_valid],
+      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
+}
 
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
+void tb_rx_frontend_valid_frame_7O1(TB_Rx_frontend * tb) {
+  Vtb_rx_frontend * core = tb->core;
+  core->testcase = T_VALID_7O1;
 
   //=================================
-  //      Tick (34-37)
+  //      Tick (0)
   
-  tb->n_tick(4);
+  tb->reset();
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
+  test_configuration_t config = {
+    .baudrate = 25000000,
+    .data = 0b10100101,
+    .ds = 0,
+    .p = 1,
+    .s = 0,
+    .inject_frame_error = 0,
+    .inject_parity_error = 0
+  };
+  tb->test_with_injected_frame(config);
 
   //`````````````````````````````````
-  //      Set inputs
+  //      Formal Checks 
   
-  core->uart_rx_i = 0;
+  CHECK("tb_rx_frontend.valid.7O1_01",
+      tb->conditions[COND_state],
+      "Failed to implement the state machine", tb->err_cycles[COND_state]);
 
-  //=================================
-  //      Tick (38)
-  
-  tb->n_tick(1);
+  CHECK("tb_rx_frontend.valid.7O1_02",
+      tb->conditions[COND_frame],
+      "Failed to implement the frame output", tb->err_cycles[COND_frame]);
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_frame,  (core->frame_o == 0b10100101));
-  tb->check(COND_errors, (core->parity_err_o == 0) &&
-                         (core->frame_err_o == 0));
-  tb->check(COND_valid, (core->output_valid_o == 1));
+  CHECK("tb_rx_frontend.valid.7O1_03",
+      tb->conditions[COND_errors],
+      "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
+
+  CHECK("tb_rx_frontend.valid.7O1_04",
+      tb->conditions[COND_valid],
+      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
+}
+
+void tb_rx_frontend_valid_frame_7O2(TB_Rx_frontend * tb) {
+  Vtb_rx_frontend * core = tb->core;
+  core->testcase = T_VALID_7O2;
 
   //=================================
-  //      Tick (39-41)
+  //      Tick (0)
   
-  tb->n_tick(3);
+  tb->reset();
 
   //`````````````````````````````````
   //      Checks 
   
+  test_configuration_t config = {
+    .baudrate = 25000000,
+    .data = 0b10100101,
+    .ds = 0,
+    .p = 1,
+    .s = 1,
+    .inject_frame_error = 0,
+    .inject_parity_error = 0
+  };
+  tb->test_with_injected_frame(config);
+
   //`````````````````````````````````
   //      Formal Checks 
   
-  CHECK("tb_rx_frontend.valid.7N1_01",
+  CHECK("tb_rx_frontend.valid.7O2_01",
       tb->conditions[COND_state],
       "Failed to implement the state machine", tb->err_cycles[COND_state]);
 
-  CHECK("tb_rx_frontend.valid.7N1_02",
+  CHECK("tb_rx_frontend.valid.7O2_02",
       tb->conditions[COND_frame],
       "Failed to implement the frame output", tb->err_cycles[COND_frame]);
 
-  CHECK("tb_rx_frontend.valid.7N1_03",
+  CHECK("tb_rx_frontend.valid.7O2_03",
       tb->conditions[COND_errors],
       "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
 
-  CHECK("tb_rx_frontend.valid.7N1_04",
+  CHECK("tb_rx_frontend.valid.7O2_04",
       tb->conditions[COND_valid],
       "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
 }
 
-void tb_rx_frontend_valid_frame_7N2(TB_Rx_frontend * tb) {
+void tb_rx_frontend_valid_frame_8N1(TB_Rx_frontend * tb) {
   Vtb_rx_frontend * core = tb->core;
-  core->testcase = T_VALID_7N2;
+  core->testcase = T_VALID_8N1;
 
   //=================================
   //      Tick (0)
@@ -365,3030 +546,305 @@ void tb_rx_frontend_valid_frame_7N2(TB_Rx_frontend * tb) {
   tb->reset();
 
   //`````````````````````````````````
-  //      Set inputs
-  
-  core->cr_acc_incr_i = (65535/4);
-  core->cr_ds_i = 0;
-  core->cr_p_i = 0;
-  core->cr_s_i = 1;
-
-  //=================================
-  //      Tick (1)
+  //      Checks 
   
-  tb->tick();
+  test_configuration_t config = {
+    .baudrate = 25000000,
+    .data = 0b10100101,
+    .ds = 1,
+    .p = 0,
+    .s = 0,
+    .inject_frame_error = 0,
+    .inject_parity_error = 0
+  };
+  tb->test_with_injected_frame(config);
 
   //`````````````````````````````````
-  //      Set inputs
+  //      Formal Checks 
   
-  core->uart_rx_i = 0;
+  CHECK("tb_rx_frontend.valid.8N1_01",
+      tb->conditions[COND_state],
+      "Failed to implement the state machine", tb->err_cycles[COND_state]);
 
-  //=================================
-  //      Tick (2-3)
-  
-  tb->n_tick(2);
+  CHECK("tb_rx_frontend.valid.8N1_02",
+      tb->conditions[COND_frame],
+      "Failed to implement the frame output", tb->err_cycles[COND_frame]);
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_valid, (core->output_valid_o == 0));
+  CHECK("tb_rx_frontend.valid.8N1_03",
+      tb->conditions[COND_errors],
+      "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
+
+  CHECK("tb_rx_frontend.valid.8N1_04",
+      tb->conditions[COND_valid],
+      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
+}
+
+void tb_rx_frontend_valid_frame_8N2(TB_Rx_frontend * tb) {
+  Vtb_rx_frontend * core = tb->core;
+  core->testcase = T_VALID_8N2;
 
   //=================================
-  //      Tick (4-5)
+  //      Tick (0)
   
-  tb->n_tick(2);
+  tb->reset();
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_START));
-  tb->check(COND_valid, (core->output_valid_o == 0));
+  test_configuration_t config = {
+    .baudrate = 25000000,
+    .data = 0b10100101,
+    .ds = 1,
+    .p = 0,
+    .s = 1,
+    .inject_frame_error = 0,
+    .inject_parity_error = 0
+  };
+  tb->test_with_injected_frame(config);
 
   //`````````````````````````````````
-  //      Set inputs
+  //      Formal Checks 
   
-  core->uart_rx_i = 1;
+  CHECK("tb_rx_frontend.valid.8N2_01",
+      tb->conditions[COND_state],
+      "Failed to implement the state machine", tb->err_cycles[COND_state]);
 
-  //=================================
-  //      Tick (6-7)
-  
-  tb->n_tick(2);
+  CHECK("tb_rx_frontend.valid.8N2_02",
+      tb->conditions[COND_frame],
+      "Failed to implement the frame output", tb->err_cycles[COND_frame]);
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
+  CHECK("tb_rx_frontend.valid.8N2_03",
+      tb->conditions[COND_errors],
+      "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
 
-  //=================================
-  //      Tick (8-9)
-  
-  tb->n_tick(2);
+  CHECK("tb_rx_frontend.valid.8N2_04",
+      tb->conditions[COND_valid],
+      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
+}
 
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
+void tb_rx_frontend_valid_frame_8E1(TB_Rx_frontend * tb) {
+  Vtb_rx_frontend * core = tb->core;
+  core->testcase = T_VALID_8E1;
 
   //=================================
-  //      Tick (10-13)
+  //      Tick (0)
   
-  tb->n_tick(4);
+  tb->reset();
 
   //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (14-17)
+  //      Checks 
   
-  tb->n_tick(4);
+  test_configuration_t config = {
+    .baudrate = 25000000,
+    .data = 0b10100101,
+    .ds = 1,
+    .p = 2,
+    .s = 0,
+    .inject_frame_error = 0,
+    .inject_parity_error = 0
+  };
+  tb->test_with_injected_frame(config);
 
   //`````````````````````````````````
-  //      Set inputs
+  //      Formal Checks 
   
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (18-21)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (22-25)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (26-29)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (30-33)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (34-37)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (38-41)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (42)
-  
-  tb->n_tick(1);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_frame,  (core->frame_o == 0b110100101));
-  tb->check(COND_errors, (core->parity_err_o == 0) &&
-                         (core->frame_err_o == 0));
-  tb->check(COND_valid, (core->output_valid_o == 1));
-
-  //=================================
-  //      Tick (43-45)
-  
-  tb->n_tick(3);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  //`````````````````````````````````
-  //      Formal Checks 
-  
-  CHECK("tb_rx_frontend.valid.7N2_01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
-
-  CHECK("tb_rx_frontend.valid.7N2_02",
-      tb->conditions[COND_frame],
-      "Failed to implement the frame output", tb->err_cycles[COND_frame]);
-
-  CHECK("tb_rx_frontend.valid.7N2_03",
-      tb->conditions[COND_errors],
-      "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
-
-  CHECK("tb_rx_frontend.valid.7N2_04",
-      tb->conditions[COND_valid],
-      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
-}
-
-void tb_rx_frontend_valid_frame_7E1(TB_Rx_frontend * tb) {
-  Vtb_rx_frontend * core = tb->core;
-  core->testcase = T_VALID_7E1;
-
-  //=================================
-  //      Tick (0)
-  
-  tb->reset();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->cr_acc_incr_i = (65535/4);
-  core->cr_ds_i = 0;
-  core->cr_p_i = 2;
-  core->cr_s_i = 0;
-
-  //=================================
-  //      Tick (1)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (2-3)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (4-5)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_START));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (6-7)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (8-9)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (10-13)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (14-17)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (18-21)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (22-25)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (26-29)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (30-33)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (34-37)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (38-41)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (42)
-  
-  tb->n_tick(1);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_frame,  (core->frame_o == 0b110100101));
-  tb->check(COND_errors, (core->parity_err_o == 0) &&
-                         (core->frame_err_o == 0));
-  tb->check(COND_valid, (core->output_valid_o == 1));
-
-  //=================================
-  //      Tick (43-45)
-  
-  tb->n_tick(3);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  //`````````````````````````````````
-  //      Formal Checks 
-  
-  CHECK("tb_rx_frontend.valid.7E1_01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
-
-  CHECK("tb_rx_frontend.valid.7E1_02",
-      tb->conditions[COND_frame],
-      "Failed to implement the frame output", tb->err_cycles[COND_frame]);
-
-  CHECK("tb_rx_frontend.valid.7E1_03",
-      tb->conditions[COND_errors],
-      "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
-
-  CHECK("tb_rx_frontend.valid.7E1_04",
-      tb->conditions[COND_valid],
-      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
-}
-
-void tb_rx_frontend_valid_frame_7E2(TB_Rx_frontend * tb) {
-  Vtb_rx_frontend * core = tb->core;
-  core->testcase = T_VALID_7E2;
-
-  //=================================
-  //      Tick (0)
-  
-  tb->reset();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->cr_acc_incr_i = (65535/4);
-  core->cr_ds_i = 0;
-  core->cr_p_i = 2;
-  core->cr_s_i = 1;
-
-  //=================================
-  //      Tick (1)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (2-3)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (4-5)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_START));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (6-7)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (8-9)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (10-13)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (14-17)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (18-21)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (22-25)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (26-29)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (30-33)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (34-37)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (38-41)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (42-45)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (46)
-  
-  tb->n_tick(1);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_frame,  (core->frame_o == 0b1110100101));
-  tb->check(COND_errors, (core->parity_err_o == 0) &&
-                         (core->frame_err_o == 0));
-  tb->check(COND_valid, (core->output_valid_o == 1));
-
-  //=================================
-  //      Tick (47-49)
-  
-  tb->n_tick(3);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  //`````````````````````````````````
-  //      Formal Checks 
-  
-  CHECK("tb_rx_frontend.valid.7E2_01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
-
-  CHECK("tb_rx_frontend.valid.7E2_02",
-      tb->conditions[COND_frame],
-      "Failed to implement the frame output", tb->err_cycles[COND_frame]);
-
-  CHECK("tb_rx_frontend.valid.7E2_03",
-      tb->conditions[COND_errors],
-      "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
-
-  CHECK("tb_rx_frontend.valid.7E2_04",
-      tb->conditions[COND_valid],
-      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
-}
-
-void tb_rx_frontend_valid_frame_7O1(TB_Rx_frontend * tb) {
-  Vtb_rx_frontend * core = tb->core;
-  core->testcase = T_VALID_7O1;
-
-  //=================================
-  //      Tick (0)
-  
-  tb->reset();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->cr_acc_incr_i = (65535/4);
-  core->cr_ds_i = 0;
-  core->cr_p_i = 1;
-  core->cr_s_i = 0;
-
-  //=================================
-  //      Tick (1)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (2-3)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (4-5)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_START));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (6-7)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (8-9)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (10-13)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (14-17)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (18-21)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (22-25)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (26-29)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (30-33)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (34-37)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (38-41)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (42)
-  
-  tb->n_tick(1);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_frame,  (core->frame_o == 0b100100101));
-  tb->check(COND_errors, (core->parity_err_o == 0) &&
-                         (core->frame_err_o == 0));
-  tb->check(COND_valid, (core->output_valid_o == 1));
-
-  //=================================
-  //      Tick (43-45)
-  
-  tb->n_tick(3);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  //`````````````````````````````````
-  //      Formal Checks 
-  
-  CHECK("tb_rx_frontend.valid.7O1_01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
-
-  CHECK("tb_rx_frontend.valid.7O1_02",
-      tb->conditions[COND_frame],
-      "Failed to implement the frame output", tb->err_cycles[COND_frame]);
-
-  CHECK("tb_rx_frontend.valid.7O1_03",
-      tb->conditions[COND_errors],
-      "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
-
-  CHECK("tb_rx_frontend.valid.7O1_04",
-      tb->conditions[COND_valid],
-      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
-}
-
-void tb_rx_frontend_valid_frame_7O2(TB_Rx_frontend * tb) {
-  Vtb_rx_frontend * core = tb->core;
-  core->testcase = T_VALID_7O2;
-
-  //=================================
-  //      Tick (0)
-  
-  tb->reset();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->cr_acc_incr_i = (65535/4);
-  core->cr_ds_i = 0;
-  core->cr_p_i = 1;
-  core->cr_s_i = 1;
-
-  //=================================
-  //      Tick (1)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (2-3)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (4-5)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_START));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (6-7)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (8-9)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (10-13)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (14-17)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (18-21)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (22-25)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (26-29)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (30-33)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (34-37)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (38-41)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (42-45)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (46)
-  
-  tb->n_tick(1);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_frame,  (core->frame_o == 0b1100100101));
-  tb->check(COND_errors, (core->parity_err_o == 0) &&
-                         (core->frame_err_o == 0));
-  tb->check(COND_valid, (core->output_valid_o == 1));
-
-  //=================================
-  //      Tick (47-49)
-  
-  tb->n_tick(3);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  //`````````````````````````````````
-  //      Formal Checks 
-  
-  CHECK("tb_rx_frontend.valid.7O2_01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
-
-  CHECK("tb_rx_frontend.valid.7O2_02",
-      tb->conditions[COND_frame],
-      "Failed to implement the frame output", tb->err_cycles[COND_frame]);
-
-  CHECK("tb_rx_frontend.valid.7O2_03",
-      tb->conditions[COND_errors],
-      "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
-
-  CHECK("tb_rx_frontend.valid.7O2_04",
-      tb->conditions[COND_valid],
-      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
-}
-
-void tb_rx_frontend_valid_frame_8N1(TB_Rx_frontend * tb) {
-  Vtb_rx_frontend * core = tb->core;
-  core->testcase = T_VALID_8N1;
-
-  //=================================
-  //      Tick (0)
-  
-  tb->reset();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->cr_acc_incr_i = (65535/4);
-  core->cr_ds_i = 1;
-  core->cr_p_i = 0;
-  core->cr_s_i = 0;
-
-  //=================================
-  //      Tick (1)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (2-3)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (4-5)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_START));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (6-7)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (8-9)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (10-13)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (14-17)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (18-21)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (22-25)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (26-29)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (30-33)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (34-37)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (38-41)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (42)
-  
-  tb->n_tick(1);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_frame,  (core->frame_o == 0b110100101));
-  tb->check(COND_errors, (core->parity_err_o == 0) &&
-                         (core->frame_err_o == 0));
-  tb->check(COND_valid, (core->output_valid_o == 1));
-
-  //=================================
-  //      Tick (43-45)
-  
-  tb->n_tick(3);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  //`````````````````````````````````
-  //      Formal Checks 
-  
-  CHECK("tb_rx_frontend.valid.8N1_01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
-
-  CHECK("tb_rx_frontend.valid.8N1_02",
-      tb->conditions[COND_frame],
-      "Failed to implement the frame output", tb->err_cycles[COND_frame]);
-
-  CHECK("tb_rx_frontend.valid.8N1_03",
-      tb->conditions[COND_errors],
-      "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
-
-  CHECK("tb_rx_frontend.valid.8N1_04",
-      tb->conditions[COND_valid],
-      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
-}
-
-void tb_rx_frontend_valid_frame_8N2(TB_Rx_frontend * tb) {
-  Vtb_rx_frontend * core = tb->core;
-  core->testcase = T_VALID_8N2;
-
-  //=================================
-  //      Tick (0)
-  
-  tb->reset();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->cr_acc_incr_i = (65535/4);
-  core->cr_ds_i = 1;
-  core->cr_p_i = 0;
-  core->cr_s_i = 1;
-
-  //=================================
-  //      Tick (1)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (2-3)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (4-5)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_START));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (6-7)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (8-9)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (10-13)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (14-17)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (18-21)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (22-25)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (26-29)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (30-33)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (34-37)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (38-41)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (42-45)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (46)
-  
-  tb->n_tick(1);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_frame,  (core->frame_o == 0b1110100101));
-  tb->check(COND_errors, (core->parity_err_o == 0) &&
-                         (core->frame_err_o == 0));
-  tb->check(COND_valid, (core->output_valid_o == 1));
-
-  //=================================
-  //      Tick (47-49)
-  
-  tb->n_tick(3);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  //`````````````````````````````````
-  //      Formal Checks 
-  
-  CHECK("tb_rx_frontend.valid.8N2_01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
-
-  CHECK("tb_rx_frontend.valid.8N2_02",
-      tb->conditions[COND_frame],
-      "Failed to implement the frame output", tb->err_cycles[COND_frame]);
-
-  CHECK("tb_rx_frontend.valid.8N2_03",
-      tb->conditions[COND_errors],
-      "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
-
-  CHECK("tb_rx_frontend.valid.8N2_04",
-      tb->conditions[COND_valid],
-      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
-}
-
-void tb_rx_frontend_valid_frame_8E1(TB_Rx_frontend * tb) {
-  Vtb_rx_frontend * core = tb->core;
-  core->testcase = T_VALID_8E1;
-
-  //=================================
-  //      Tick (0)
-  
-  tb->reset();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->cr_acc_incr_i = (65535/4);
-  core->cr_ds_i = 1;
-  core->cr_p_i = 2;
-  core->cr_s_i = 0;
-
-  //=================================
-  //      Tick (1)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (2-3)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (4-5)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_START));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (6-7)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (8-9)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (10-13)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (14-17)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (18-21)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (22-25)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (26-29)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (30-33)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (34-37)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (38-41)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (42-45)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (46)
-  
-  tb->n_tick(1);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_frame,  (core->frame_o == 0b1010100101));
-  tb->check(COND_errors, (core->parity_err_o == 0) &&
-                         (core->frame_err_o == 0));
-  tb->check(COND_valid, (core->output_valid_o == 1));
-
-  //=================================
-  //      Tick (47-49)
-  
-  tb->n_tick(3);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  //`````````````````````````````````
-  //      Formal Checks 
-  
-  CHECK("tb_rx_frontend.valid.8E1_01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
-
-  CHECK("tb_rx_frontend.valid.8E1_02",
-      tb->conditions[COND_frame],
-      "Failed to implement the frame output", tb->err_cycles[COND_frame]);
-
-  CHECK("tb_rx_frontend.valid.8E1_03",
-      tb->conditions[COND_errors],
-      "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
-
-  CHECK("tb_rx_frontend.valid.8E1_04",
-      tb->conditions[COND_valid],
-      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
-}
-
-void tb_rx_frontend_valid_frame_8E2(TB_Rx_frontend * tb) {
-  Vtb_rx_frontend * core = tb->core;
-  core->testcase = T_VALID_8E2;
-
-  //=================================
-  //      Tick (0)
-  
-  tb->reset();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->cr_acc_incr_i = (65535/4);
-  core->cr_ds_i = 1;
-  core->cr_p_i = 2;
-  core->cr_s_i = 1;
-
-  //=================================
-  //      Tick (1)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (2-3)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (4-5)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_START));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (6-7)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (8-9)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (10-13)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (14-17)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (18-21)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (22-25)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (26-29)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (30-33)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (34-37)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (38-41)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (42-45)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (46-49)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (50)
-  
-  tb->n_tick(1);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_frame,  (core->frame_o == 0b11010100101));
-  tb->check(COND_errors, (core->parity_err_o == 0) &&
-                         (core->frame_err_o == 0));
-  tb->check(COND_valid, (core->output_valid_o == 1));
-
-  //=================================
-  //      Tick (51-53)
-  
-  tb->n_tick(3);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  //`````````````````````````````````
-  //      Formal Checks 
-  
-  CHECK("tb_rx_frontend.valid.8E2_01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
-
-  CHECK("tb_rx_frontend.valid.8E2_02",
-      tb->conditions[COND_frame],
-      "Failed to implement the frame output", tb->err_cycles[COND_frame]);
-
-  CHECK("tb_rx_frontend.valid.8E2_03",
-      tb->conditions[COND_errors],
-      "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
-
-  CHECK("tb_rx_frontend.valid.8E2_04",
-      tb->conditions[COND_valid],
-      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
-}
-
-void tb_rx_frontend_valid_frame_8O1(TB_Rx_frontend * tb) {
-  Vtb_rx_frontend * core = tb->core;
-  core->testcase = T_VALID_8O1;
-
-  //=================================
-  //      Tick (0)
-  
-  tb->reset();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->cr_acc_incr_i = (65535/4);
-  core->cr_ds_i = 1;
-  core->cr_p_i = 1;
-  core->cr_s_i = 0;
-
-  //=================================
-  //      Tick (1)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (2-3)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (4-5)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_START));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (6-7)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (8-9)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (10-13)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (14-17)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (18-21)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (22-25)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (26-29)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (30-33)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (34-37)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (38-41)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (42-45)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (46)
-  
-  tb->n_tick(1);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_frame,  (core->frame_o == 0b1110100101));
-  tb->check(COND_errors, (core->parity_err_o == 0) &&
-                         (core->frame_err_o == 0));
-  tb->check(COND_valid, (core->output_valid_o == 1));
-
-  //=================================
-  //      Tick (47-49)
-  
-  tb->n_tick(3);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  //`````````````````````````````````
-  //      Formal Checks 
-  
-  CHECK("tb_rx_frontend.valid.8O1_01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
-
-  CHECK("tb_rx_frontend.valid.8O1_02",
-      tb->conditions[COND_frame],
-      "Failed to implement the frame output", tb->err_cycles[COND_frame]);
-
-  CHECK("tb_rx_frontend.valid.8O1_03",
-      tb->conditions[COND_errors],
-      "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
-
-  CHECK("tb_rx_frontend.valid.8O1_04",
-      tb->conditions[COND_valid],
-      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
-}
-
-void tb_rx_frontend_valid_frame_8O2(TB_Rx_frontend * tb) {
-  Vtb_rx_frontend * core = tb->core;
-  core->testcase = T_VALID_8O2;
-
-  //=================================
-  //      Tick (0)
-  
-  tb->reset();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->cr_acc_incr_i = (65535/4);
-  core->cr_ds_i = 1;
-  core->cr_p_i = 1;
-  core->cr_s_i = 1;
-
-  //=================================
-  //      Tick (1)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (2-3)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (4-5)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_START));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (6-7)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (8-9)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (10-13)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (14-17)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (18-21)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (22-25)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (26-29)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (30-33)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (34-37)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (38-41)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (42-45)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (46-49)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (50)
-  
-  tb->n_tick(1);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_frame,  (core->frame_o == 0b11110100101));
-  tb->check(COND_errors, (core->parity_err_o == 0) &&
-                         (core->frame_err_o == 0));
-  tb->check(COND_valid, (core->output_valid_o == 1));
-
-  //=================================
-  //      Tick (51-53)
-  
-  tb->n_tick(3);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  //`````````````````````````````````
-  //      Formal Checks 
-  
-  CHECK("tb_rx_frontend.valid.8O2_01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
-
-  CHECK("tb_rx_frontend.valid.8O2_02",
-      tb->conditions[COND_frame],
-      "Failed to implement the frame output", tb->err_cycles[COND_frame]);
-
-  CHECK("tb_rx_frontend.valid.8O2_03",
-      tb->conditions[COND_errors],
-      "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
-
-  CHECK("tb_rx_frontend.valid.8O2_04",
-      tb->conditions[COND_valid],
-      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
-}
-
-void tb_rx_frontend_baudrate(TB_Rx_frontend * tb) {
-  Vtb_rx_frontend * core = tb->core;
-  core->testcase = T_BAUDRATE;
-
-  //=================================
-  //      Tick (0)
-  
-  tb->reset();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->cr_acc_incr_i = (65535/100);
-  core->cr_ds_i = 0;
-  core->cr_p_i = 0;
-  core->cr_s_i = 0;
-
-  //=================================
-  //      Tick (1)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (2-4)
-  
-  tb->n_tick(3); // 3 cycle delay due to metastability countermeasures
-
-  //=================================
-  //      Tick (5)
-  
-  tb->n_tick(1); // 1 cycle delay between idle and start
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_START));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (6-54)
-  
-  tb->n_tick(49);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (55-104)
-  
-  tb->n_tick(50);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (105-154)
-  
-  tb->n_tick(50);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (155-204)
-  
-  tb->n_tick(50);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (205-304)
-  
-  tb->n_tick(100);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (305-404)
-  
-  tb->n_tick(100);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (405-504)
-  
-  tb->n_tick(100);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (505-604)
-  
-  tb->n_tick(100);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (605-704)
-  
-  tb->n_tick(100);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (705-804)
-  
-  tb->n_tick(100);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (805-854)
-  
-  tb->n_tick(50);
-
-  //=================================
-  //      Tick (855-854)
-  
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_frame,  (core->frame_o == 0b10100101));
-  tb->check(COND_errors, (core->parity_err_o == 0) &&
-                         (core->frame_err_o == 0));
-  tb->check(COND_valid, (core->output_valid_o == 1));
-
-  //=================================
-  //      Tick (955-904)
-  
-  tb->n_tick(50);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (905)
-  
-  tb->n_tick(1);
-
-  //=================================
-  //      Tick (906-954)
-  
-  tb->n_tick(49);
-
-  //`````````````````````````````````
-  //      Formal Checks 
-  
-  CHECK("tb_rx_frontend.baudrate.01",
+  CHECK("tb_rx_frontend.valid.8E1_01",
       tb->conditions[COND_state],
       "Failed to implement the state machine", tb->err_cycles[COND_state]);
 
-  CHECK("tb_rx_frontend.baudrate.02",
+  CHECK("tb_rx_frontend.valid.8E1_02",
       tb->conditions[COND_frame],
       "Failed to implement the frame output", tb->err_cycles[COND_frame]);
 
-  CHECK("tb_rx_frontend.baudrate.03",
-      tb->conditions[COND_errors],
-      "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
-
-  CHECK("tb_rx_frontend.baudrate.04",
-      tb->conditions[COND_valid],
-      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
-}
-
-void tb_rx_frontend_parity_even(TB_Rx_frontend * tb) {
-  Vtb_rx_frontend * core = tb->core;
-  core->testcase = T_PARITY_EVEN;
-
-  //=================================
-  //      Tick (0)
-  
-  tb->reset();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->cr_acc_incr_i = (65535/4);
-  core->cr_ds_i = 0;
-  core->cr_p_i = 2;
-  core->cr_s_i = 0;
-
-  //=================================
-  //      Tick (1)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (2-5)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (6-9)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (10-13)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (14-17)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (18-21)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (22-25)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (26-29)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (30-33)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (34-37)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (38-39)
-  
-  tb->n_tick(2);
-  
-  //=================================
-  //      Tick (40-42)
-  
-  tb->n_tick(3); // 3 cycle delay due to metastability countermeasures
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_errors, (core->parity_err_o == 0));
-  tb->check(COND_valid,  (core->output_valid_o == 1));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (43-46)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (47-50)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (51-54)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (55-58)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (59-62)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (63-66)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (67-70)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (71-74)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (75-78)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (79-80)
-  
-  tb->n_tick(2);
-  
-  //=================================
-  //      Tick (81-83)
-  
-  tb->n_tick(3); // 3 cycle delay due to metastability countermeasures
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_errors, (core->parity_err_o == 0));
-  tb->check(COND_valid,  (core->output_valid_o == 1));
-
-  //`````````````````````````````````
-  //      Formal Checks 
-  
-  CHECK("tb_rx_frontend.parity.EVEN_01",
+  CHECK("tb_rx_frontend.valid.8E1_03",
       tb->conditions[COND_errors],
       "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
 
-  CHECK("tb_rx_frontend.parity.EVEN_02",
+  CHECK("tb_rx_frontend.valid.8E1_04",
       tb->conditions[COND_valid],
-      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
-}
-
-void tb_rx_frontend_parity_odd(TB_Rx_frontend * tb) {
-  Vtb_rx_frontend * core = tb->core;
-  core->testcase = T_PARITY_ODD;
-
-  //=================================
-  //      Tick (0)
-  
-  tb->reset();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->cr_acc_incr_i = (65535/4);
-  core->cr_ds_i = 0;
-  core->cr_p_i = 1;
-  core->cr_s_i = 0;
-
-  //=================================
-  //      Tick (1)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (2-5)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (6-9)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (10-13)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (14-17)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (18-21)
-  
-  tb->n_tick(4);
+      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
+}
 
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
+void tb_rx_frontend_valid_frame_8E2(TB_Rx_frontend * tb) {
+  Vtb_rx_frontend * core = tb->core;
+  core->testcase = T_VALID_8E2;
 
   //=================================
-  //      Tick (22-25)
+  //      Tick (0)
   
-  tb->n_tick(4);
+  tb->reset();
 
   //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (26-29)
+  //      Checks 
   
-  tb->n_tick(4);
+  test_configuration_t config = {
+    .baudrate = 25000000,
+    .data = 0b10100101,
+    .ds = 1,
+    .p = 2,
+    .s = 1,
+    .inject_frame_error = 0,
+    .inject_parity_error = 0
+  };
+  tb->test_with_injected_frame(config);
 
   //`````````````````````````````````
-  //      Set inputs
+  //      Formal Checks 
   
-  core->uart_rx_i = 0;
+  CHECK("tb_rx_frontend.valid.8E2_01",
+      tb->conditions[COND_state],
+      "Failed to implement the state machine", tb->err_cycles[COND_state]);
 
-  //=================================
-  //      Tick (30-33)
-  
-  tb->n_tick(4);
+  CHECK("tb_rx_frontend.valid.8E2_02",
+      tb->conditions[COND_frame],
+      "Failed to implement the frame output", tb->err_cycles[COND_frame]);
 
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
+  CHECK("tb_rx_frontend.valid.8E2_03",
+      tb->conditions[COND_errors],
+      "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
 
-  //=================================
-  //      Tick (34-37)
-  
-  tb->n_tick(4);
+  CHECK("tb_rx_frontend.valid.8E2_04",
+      tb->conditions[COND_valid],
+      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
+}
 
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
+void tb_rx_frontend_valid_frame_8O1(TB_Rx_frontend * tb) {
+  Vtb_rx_frontend * core = tb->core;
+  core->testcase = T_VALID_8O1;
 
   //=================================
-  //      Tick (38-39)
-  
-  tb->n_tick(2);
-  
-  //=================================
-  //      Tick (40-42)
+  //      Tick (0)
   
-  tb->n_tick(3); // 3 cycle delay due to metastability countermeasures
+  tb->reset();
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_errors, (core->parity_err_o == 0));
-  tb->check(COND_valid,  (core->output_valid_o == 1));
+  test_configuration_t config = {
+    .baudrate = 25000000,
+    .data = 0b10100101,
+    .ds = 1,
+    .p = 1,
+    .s = 0,
+    .inject_frame_error = 0,
+    .inject_parity_error = 0
+  };
+  tb->test_with_injected_frame(config);
 
   //`````````````````````````````````
-  //      Set inputs
+  //      Formal Checks 
   
-  core->uart_rx_i = 0;
+  CHECK("tb_rx_frontend.valid.8O1_01",
+      tb->conditions[COND_state],
+      "Failed to implement the state machine", tb->err_cycles[COND_state]);
 
-  //=================================
-  //      Tick (43-46)
-  
-  tb->n_tick(4);
+  CHECK("tb_rx_frontend.valid.8O1_02",
+      tb->conditions[COND_frame],
+      "Failed to implement the frame output", tb->err_cycles[COND_frame]);
 
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
+  CHECK("tb_rx_frontend.valid.8O1_03",
+      tb->conditions[COND_errors],
+      "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
 
-  //=================================
-  //      Tick (47-50)
-  
-  tb->n_tick(4);
+  CHECK("tb_rx_frontend.valid.8O1_04",
+      tb->conditions[COND_valid],
+      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
+}
 
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
+void tb_rx_frontend_valid_frame_8O2(TB_Rx_frontend * tb) {
+  Vtb_rx_frontend * core = tb->core;
+  core->testcase = T_VALID_8O2;
 
   //=================================
-  //      Tick (51-54)
+  //      Tick (0)
   
-  tb->n_tick(4);
+  tb->reset();
 
   //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (55-58)
+  //      Checks 
   
-  tb->n_tick(4);
+  test_configuration_t config = {
+    .baudrate = 25000000,
+    .data = 0b10100101,
+    .ds = 1,
+    .p = 1,
+    .s = 1,
+    .inject_frame_error = 0,
+    .inject_parity_error = 0
+  };
+  tb->test_with_injected_frame(config);
 
   //`````````````````````````````````
-  //      Set inputs
+  //      Formal Checks 
   
-  core->uart_rx_i = 1;
+  CHECK("tb_rx_frontend.valid.8O2_01",
+      tb->conditions[COND_state],
+      "Failed to implement the state machine", tb->err_cycles[COND_state]);
 
-  //=================================
-  //      Tick (59-62)
-  
-  tb->n_tick(4);
+  CHECK("tb_rx_frontend.valid.8O2_02",
+      tb->conditions[COND_frame],
+      "Failed to implement the frame output", tb->err_cycles[COND_frame]);
 
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
+  CHECK("tb_rx_frontend.valid.8O2_03",
+      tb->conditions[COND_errors],
+      "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
 
-  //=================================
-  //      Tick (63-66)
-  
-  tb->n_tick(4);
+  CHECK("tb_rx_frontend.valid.8O2_04",
+      tb->conditions[COND_valid],
+      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
+}
 
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
+void tb_rx_frontend_parity_even(TB_Rx_frontend * tb) {
+  Vtb_rx_frontend * core = tb->core;
+  core->testcase = T_PARITY_EVEN;
 
   //=================================
-  //      Tick (67-70)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
+  //      Tick (0)
   
-  core->uart_rx_i = 1;
+  tb->reset();
 
-  //=================================
-  //      Tick (71-74)
-  
-  tb->n_tick(4);
+  test_configuration_t config = {
+    .baudrate = 25000000,
+    .data = 0b10100101,
+    .ds = 0,
+    .p = 2,
+    .s = 0,
+    .inject_frame_error = 0,
+    .inject_parity_error = 1
+  };
+  tb->test_with_injected_frame(config);
 
   //`````````````````````````````````
-  //      Set inputs
+  //      Formal Checks 
   
-  core->uart_rx_i = 1;
+  CHECK("tb_rx_frontend.parity.EVEN_01",
+      tb->conditions[COND_errors],
+      "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
 
-  //=================================
-  //      Tick (75-78)
-  
-  tb->n_tick(4);
+  CHECK("tb_rx_frontend.parity.EVEN_02",
+      tb->conditions[COND_valid],
+      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
+}
 
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
+void tb_rx_frontend_parity_odd(TB_Rx_frontend * tb) {
+  Vtb_rx_frontend * core = tb->core;
+  core->testcase = T_PARITY_ODD;
 
   //=================================
-  //      Tick (79-80)
-  
-  tb->n_tick(2);
-  
-  //=================================
-  //      Tick (81-83)
+  //      Tick (0)
   
-  tb->n_tick(3); // 3 cycle delay due to metastability countermeasures
+  tb->reset();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_errors, (core->parity_err_o == 1));
-  tb->check(COND_valid,  (core->output_valid_o == 1));
+  test_configuration_t config = {
+    .baudrate = 25000000,
+    .data = 0b10100101,
+    .ds = 0,
+    .p = 1,
+    .s = 0,
+    .inject_frame_error = 0,
+    .inject_parity_error = 1
+  };
+  tb->test_with_injected_frame(config);
 
   //`````````````````````````````````
   //      Formal Checks 
@@ -3409,177 +865,86 @@ void tb_rx_frontend_framing(TB_Rx_frontend * tb) {
   //=================================
   //      Tick (1)
   
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (2-3)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_IDLE));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (4-5)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_START));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (6-7)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
-
-  //=================================
-  //      Tick (8-9)
-  
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (10-13)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (14-17)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (18-21)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (22-25)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (26-29)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (30-33)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 1;
+  tb->reset();
 
-  //=================================
-  //      Tick (34-37)
-  
-  tb->n_tick(4);
+  test_configuration_t config = {
+    .baudrate = 25000000,
+    .data = 0b10100101,
+    .ds = 0,
+    .p = 0,
+    .s = 0,
+    .inject_frame_error = 1,
+    .inject_parity_error = 0
+  };
+  tb->test_with_injected_frame(config);
 
   //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (38-41)
+  //      Formal Checks 
   
-  tb->n_tick(4);
+  CHECK("tb_rx_frontend.framing.01",
+      tb->conditions[COND_state],
+      "Failed to implement the state machine", tb->err_cycles[COND_state]);
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_state, (core->tb_rx_frontend->dut->state_q == S_DATA));
-  tb->check(COND_valid, (core->output_valid_o == 0));
+  CHECK("tb_rx_frontend.framing.02",
+      tb->conditions[COND_errors],
+      "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
 
-  //`````````````````````````````````
-  //      Set inputs
-  
-  core->uart_rx_i = 0;
+  CHECK("tb_rx_frontend.framing.03",
+      tb->conditions[COND_valid],
+      "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
+}
 
-  //=================================
-  //      Tick (42)
-  
-  tb->n_tick(1);
+void tb_rx_frontend_baudrate(TB_Rx_frontend * tb) {
+  Vtb_rx_frontend * core = tb->core;
+  core->testcase = T_BAUDRATE;
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_errors, (core->frame_err_o == 1));
+  tb->reset();
 
-  //=================================
-  //      Tick (43-45)
-  
-  tb->n_tick(3);
+  uint32_t baudrates[] = {
+    4800,
+    9600,
+    19200,
+    38400,
+    57600,
+    115200,
+    230400,
+    460800,
+    921600,
+    1000000,
+    2000000,
+    3000000
+  };
+  size_t num_baudrates = sizeof(baudrates)/sizeof(uint32_t);
+
+  for(size_t i = 0; i < num_baudrates; i++) {
+    test_configuration_t config = {
+      .baudrate = baudrates[i],
+      .data = 0b10100101,
+      .ds = 1,
+      .p = 1,
+      .s = 1,
+      .inject_frame_error = 0,
+      .inject_parity_error = 0
+    };
+    tb->test_with_injected_frame(config);
+  }
 
-  //`````````````````````````````````
-  //      Checks 
-  
   //`````````````````````````````````
   //      Formal Checks 
   
-  CHECK("tb_rx_frontend.framing.01",
+  CHECK("tb_rx_frontend.baudrate.01",
       tb->conditions[COND_state],
       "Failed to implement the state machine", tb->err_cycles[COND_state]);
 
-  CHECK("tb_rx_frontend.framing.02",
+  CHECK("tb_rx_frontend.baudrate.02",
+      tb->conditions[COND_frame],
+      "Failed to implement the frame output", tb->err_cycles[COND_frame]);
+
+  CHECK("tb_rx_frontend.baudrate.03",
       tb->conditions[COND_errors],
       "Failed to implement the errors computation", tb->err_cycles[COND_errors]);
 
-  CHECK("tb_rx_frontend.framing.03",
+  CHECK("tb_rx_frontend.baudrate.04",
       tb->conditions[COND_valid],
       "Failed to implement the valid signal", tb->err_cycles[COND_valid]);
 }
@@ -3589,6 +954,7 @@ int main(int argc, char ** argv, char ** env) {
   Verilated::traceEverOn(true);
 
   bool verbose = parse_verbose(argc, argv);
+  verbose = 1;
 
   TB_Rx_frontend * tb = new TB_Rx_frontend;
   tb->open_trace("waves/rx_frontend.vcd");
@@ -3596,6 +962,9 @@ int main(int argc, char ** argv, char ** env) {
   tb->set_debug_log(verbose);
   tb->init_conditions(__CondIdEnd);
 
+  // 24MHz
+  tb->clk_period_in_ps = 41667;
+
   /************************************************************/
 
   tb_rx_frontend_idle(tb);
@@ -3613,12 +982,12 @@ int main(int argc, char ** argv, char ** env) {
   tb_rx_frontend_valid_frame_8O1(tb);
   tb_rx_frontend_valid_frame_8O2(tb);
 
-  tb_rx_frontend_baudrate(tb);
-
   tb_rx_frontend_parity_even(tb);
   tb_rx_frontend_parity_odd(tb);
   tb_rx_frontend_framing(tb);
 
+  tb_rx_frontend_baudrate(tb);
+
   /************************************************************/
 
   printf("[RX_FRONTEND]: ");
diff --git a/tests/benches/rx_frontend/tb_rx_frontend.sv b/tests/benches/rx_frontend/tb_rx_frontend.sv
index 69cc99f..d366dbd 100644
--- a/tests/benches/rx_frontend/tb_rx_frontend.sv
+++ b/tests/benches/rx_frontend/tb_rx_frontend.sv
@@ -37,7 +37,8 @@ module tb_rx_frontend
   output  logic[10:0]   frame_o,
   output  logic         parity_err_o,
   output  logic         frame_err_o,
-  output  logic         output_valid_o
+  output  logic         output_valid_o,
+  input logic test
 );
 
 rx_frontend dut (
diff --git a/tests/benches/tx_frontend/tb_tx_frontend.cpp b/tests/benches/tx_frontend/tb_tx_frontend.cpp
index 53457fb..4f0ddff 100644
--- a/tests/benches/tx_frontend/tb_tx_frontend.cpp
+++ b/tests/benches/tx_frontend/tb_tx_frontend.cpp
@@ -2947,7 +2947,6 @@ int main(int argc, char ** argv, char ** env) {
   Verilated::traceEverOn(true);
 
   bool verbose = parse_verbose(argc, argv);
-  verbose = true;
 
   TB_Tx_frontend * tb = new TB_Tx_frontend;
   tb->open_trace("waves/tx_frontend.vcd");

From ea7d565d9f934cfde6d0352bc4e6cfe707692eff Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Cl=C3=A9ment=20Chaine?= <clement.chaine25@gmail.com>
Date: Thu, 4 Dec 2025 20:17:09 +0100
Subject: [PATCH 07/15] Update unit tests for the top module

---
 config/gtkwave/config/ecap5_dwbuart.gtkw      |  35 +-
 src/ecap5_dwbuart.sv                          |  47 ++-
 .../ecap5_dwbuart/tb_ecap5_dwbuart.cpp        | 365 ++++++++++--------
 .../benches/ecap5_dwbuart/tb_ecap5_dwbuart.sv |  16 +-
 4 files changed, 254 insertions(+), 209 deletions(-)

diff --git a/config/gtkwave/config/ecap5_dwbuart.gtkw b/config/gtkwave/config/ecap5_dwbuart.gtkw
index dd60a9d..a563fd9 100644
--- a/config/gtkwave/config/ecap5_dwbuart.gtkw
+++ b/config/gtkwave/config/ecap5_dwbuart.gtkw
@@ -1,15 +1,15 @@
 [*]
 [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
-[*] Wed May  8 07:33:08 2024
+[*] Thu Dec  4 18:16:15 2025
 [*]
 [dumpfile] "/Users/cchaine/Desktop/Documents/projects/.ecap5.nosync/design/wbuart/build/tests/waves/ecap5_dwbuart.vcd"
-[dumpfile_mtime] "Wed May  8 07:26:31 2024"
-[dumpfile_size] 23128
+[dumpfile_mtime] "Thu Dec  4 18:15:49 2025"
+[dumpfile_size] 67035
 [savefile] "/Users/cchaine/Desktop/Documents/projects/.ecap5.nosync/design/wbuart/config/gtkwave/config/ecap5_dwbuart.gtkw"
-[timestart] 1
-[size] 1440 783
+[timestart] 2792
+[size] 1900 935
 [pos] -1 -1
-*-6.069452 123 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+*-4.971742 2889 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 [markername] AA
 [markername] BB
 [markername] CC
@@ -39,13 +39,13 @@
 [treeopen] TOP.
 [treeopen] TOP.tb_ecap5_dwbuart.
 [treeopen] TOP.tb_ecap5_dwbuart.dut.
-[sst_width] 253
+[sst_width] 255
 [signals_width] 193
 [sst_expanded] 1
-[sst_vpaned_height] 386
+[sst_vpaned_height] 682
 @2024
 [color] 1
-^1 /Users/cchaine/Desktop/Documents/projects/.ecap5.nosync/design/wbuart/config/gtkwave/filters/ecap5_dwbuart_testcase_filter.gtkw
+^1 /Users/cchaine/Desktop/Documents/projects/.ecap5.nosync/design/wbuart/config/gtkwave/filters/ecap5_wbuart_testcase_filter.gtkw
 TOP.tb_ecap5_dwbuart.testcase[31:0]
 @28
 TOP.tb_ecap5_dwbuart.clk_i
@@ -78,22 +78,21 @@ TOP.tb_ecap5_dwbuart.wb_stall_o
 -Wishbone
 @28
 [color] 7
-TOP.tb_ecap5_dwbuart.uart_rx_i
+TOP.tb_ecap5_dwbuart.dut.uart_rx_i
 [color] 7
-TOP.tb_ecap5_dwbuart.uart_tx_o
+TOP.tb_ecap5_dwbuart.dut.uart_tx_o
 @800200
 -Registers
-@c00201
 -CR
 @22
-TOP.tb_ecap5_dwbuart.dut.cr_clk_div_q[15:0]
+TOP.tb_ecap5_dwbuart.dut.cr_acc_incr_q[15:0]
 @28
 TOP.tb_ecap5_dwbuart.dut.cr_ds_q
 TOP.tb_ecap5_dwbuart.dut.cr_p_q[1:0]
 TOP.tb_ecap5_dwbuart.dut.cr_s_q
-@1401201
+@1000200
 -CR
-@c00200
+@800200
 -SR
 @28
 TOP.tb_ecap5_dwbuart.dut.sr_fe_q
@@ -101,7 +100,7 @@ TOP.tb_ecap5_dwbuart.dut.sr_pe_q
 TOP.tb_ecap5_dwbuart.dut.sr_rxne_q
 TOP.tb_ecap5_dwbuart.dut.sr_rxoe_q
 TOP.tb_ecap5_dwbuart.dut.sr_txe_q
-@1401200
+@1000200
 -SR
 @22
 TOP.tb_ecap5_dwbuart.dut.txdr_txd_q[7:0]
@@ -115,7 +114,7 @@ TOP.tb_ecap5_dwbuart.dut.tx_done
 TOP.tb_ecap5_dwbuart.dut.rx_valid
 @22
 TOP.tb_ecap5_dwbuart.dut.rx_frame[10:0]
-@28
-TOP.tb_ecap5_dwbuart.dut.rx_parity
+@29
+TOP.tb_ecap5_dwbuart.inj_frame_error
 [pattern_trace] 1
 [pattern_trace] 0
diff --git a/src/ecap5_dwbuart.sv b/src/ecap5_dwbuart.sv
index 726fdfd..0fdf5e6 100644
--- a/src/ecap5_dwbuart.sv
+++ b/src/ecap5_dwbuart.sv
@@ -167,7 +167,7 @@ always_comb begin : register_access
   rxdr_rxd_d   = rxdr_rxd_q;
   txdr_txd_d   = txdr_txd_q;
 
-  // Set the data output for R and R/W registers
+  // Set the data output for read requests
   mem_read_data_d = 0;
   case(mem_addr[7:2])
     UART_SR:   mem_read_data_d = {27'b0, sr_pe_q, sr_fe_q, sr_rxoe_q, sr_txe_q, sr_rxne_q};
@@ -176,7 +176,7 @@ always_comb begin : register_access
     default:   mem_read_data_d = '0;
   endcase
 
-  // Set the register data for R/W and W registers
+  // Set the register data for write requests
   if(mem_write) begin
     case(mem_addr[7:2])
       UART_CR: begin
@@ -185,42 +185,41 @@ always_comb begin : register_access
         cr_s_d = mem_write_data[2];
         cr_p_d = mem_write_data[1:0];
       end
-      UART_TXDR: txdr_txd_d = mem_write_data[7:0];
+      UART_TXDR: begin
+        txdr_txd_d = mem_write_data[7:0];
+      end
       default: begin end
     endcase 
   end
 
-  // Set the TXE field
-  if(tx_done) begin
-    sr_txe_d = 1;
-  end
-
-  // Reset the TXE field
+  // Priority to the memory request
   if(mem_write && (mem_addr[7:2] == UART_TXDR)) begin
     sr_txe_d = 0;
+  end else if (tx_done) begin
+    sr_txe_d = 1;
   end
 
-  // Set the RXDR register and RXNE field
+  // Priority to the hardware
   if(rx_valid) begin
     rxdr_rxd_d = rx_frame[7:0];
     sr_rxne_d = 1;
-  end
 
-  // Reset UART_RXDR after reading
-  if(mem_read && mem_addr[7:2] == UART_RXDR) begin
+    // Errors accumulate so they are never lost
+    sr_pe_d = sr_pe_q | rx_parity_err;
+    sr_fe_d = sr_fe_q | rx_frame_err;
+    
+    // If data was read but the buffer was already full
+    if (sr_rxne_q) begin
+      sr_rxoe_d = 1;
+    end
+  // When the memory request occurs but no data was received
+  // we clear the previously received data
+  end else if(mem_read && mem_addr[7:2] == UART_RXDR) begin
     rxdr_rxd_d = '0;
     sr_rxne_d = 0;
-  end
-
-  // Receive error detection
-  if(rx_valid) begin
-    sr_pe_d = rx_parity_err;
-    sr_fe_d = rx_frame_err;
-    sr_rxoe_d = sr_rxne_q | sr_rxoe_q;
-  end
-
-  // Reset UART_SR error fields after reading UART_SR
-  if(mem_read && mem_addr[7:2] == UART_SR) begin
+  // When the memory request occurs but no data was received
+  // we clear the errors
+  end else if(mem_read && mem_addr[7:2] == UART_SR) begin
     sr_pe_d = 0;
     sr_fe_d = 0;
     sr_rxoe_d = 0;
diff --git a/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.cpp b/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.cpp
index 0c8b5a3..6a99997 100644
--- a/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.cpp
+++ b/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.cpp
@@ -77,7 +77,7 @@ class TB_Ecap5_dwbuart : public Testbench<Vtb_ecap5_dwbuart> {
     this->core->wb_stb_i = 0;
     this->core->wb_cyc_i = 0;
 
-    this->core->uart_rx_i = 1;
+//    this->core->uart_rx_i = 1;
   }
 
   void read(uint32_t addr) {
@@ -98,12 +98,6 @@ class TB_Ecap5_dwbuart : public Testbench<Vtb_ecap5_dwbuart> {
     this->core->wb_cyc_i = 1;
   }
 
-  void n_tick(int n) {
-    for(int i = 0; i < n; i++) {
-      this->tick();
-    }
-  } 
-
   uint32_t uart_sr() {
     uint32_t reg = 0;
     reg |= core->tb_ecap5_dwbuart->dut->sr_pe_q << 4;
@@ -130,31 +124,6 @@ class TB_Ecap5_dwbuart : public Testbench<Vtb_ecap5_dwbuart> {
   uint32_t uart_txdr() {
     return core->tb_ecap5_dwbuart->dut->txdr_txd_q;
   }
-
-  void send(uint32_t data, uint32_t acc_incr, uint8_t ds, uint8_t p, uint8_t s, uint8_t inject_pe, uint8_t inject_fe) {
-    // Start bit
-    this->core->uart_rx_i = 0;
-    this->n_tick(acc_incr);
-    // Data bits
-    uint8_t num_data_bits = ds ? 8 : 7;
-    uint8_t parity = p & 0x1;
-    for(int i = 0; i < num_data_bits; i++) {
-      this->core->uart_rx_i = (data >> i) & 0x1;
-      parity ^= (data >> i) & 0x1;
-      this->n_tick(acc_incr);
-    }
-    // Parity bits
-    if(p) {
-      this->core->uart_rx_i = inject_pe ? (parity ^ 1) : 0; 
-      this->n_tick(acc_incr);
-    }
-    // Stop bits
-    uint8_t num_stop_bits = s ? 2 : 1;
-    for(int i = 0; i < num_stop_bits; i++) {
-      this->core->uart_rx_i = !inject_fe;
-      this->n_tick(acc_incr);
-    }
-  }
 };
 
 void tb_ecap5_dwbuart_idle(TB_Ecap5_dwbuart * tb) {
@@ -320,7 +289,8 @@ void tb_ecap5_dwbuart_write_txdr(TB_Ecap5_dwbuart * tb) {
   //`````````````````````````````````
   //      Set inputs
 
-  uint32_t cr = (4 << 16) | (1 << 3) | 1;
+  // (2**16)/4 = 16384 = 1 bit every 4 clk cycles
+  uint32_t cr = (16384 << 16) | (1 << 3) | 1;
   tb->write(0x4, cr);
 
   //=================================
@@ -384,56 +354,14 @@ void tb_ecap5_dwbuart_write_txdr(TB_Ecap5_dwbuart * tb) {
   
   tb->_nop();
   core->wb_cyc_i = 0;
-  
-  //=================================
-  //      Tick (6-7)
-  
-  // Wait half acc_incr
-  tb->n_tick(2);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_tx, (core->uart_tx_o == 0));
-  
-  //=================================
-  //      Tick (8-11)
-  
-  tb->n_tick(4);
-
-  //=================================
-  //      Tick (11-43)
-  
-  uint8_t expected = 0xA5;
-  for(int i = 0; i < 8; i++) {
-    tb->check(COND_tx, (core->uart_tx_o == ((expected >> i) & 0x1)));
-
-    //=================================
-    //      Tick 
-    
-    tb->n_tick(4);
-  }
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_tx, (core->uart_tx_o == 1));
 
   //=================================
-  //      Tick (44-47)
-  
-  tb->n_tick(4);
-
-  //`````````````````````````````````
-  //      Checks 
+  //      Tick (6-49)
   
-  tb->check(COND_tx, (core->uart_tx_o == 1));
-
-  //=================================
-  //      Tick (48-49)
+  // 1 start bit, 8 data bits, 1 parity bit, 1 stop bit
+  uint32_t number_of_tx_bits = (1 + 8 + 1 + 1) * 4;
+  tb->n_tick(number_of_tx_bits);
   
-  tb->n_tick(2);
-
   //`````````````````````````````````
   //      Checks 
   
@@ -482,7 +410,8 @@ void tb_ecap5_dwbuart_read_rxdr(TB_Ecap5_dwbuart * tb) {
   //`````````````````````````````````
   //      Set inputs
 
-  uint32_t cr = (4 << 16) | (1 << 3) | 1;
+  // (2**16)/4 = 16384 = 1 bit every 4 clk cycles
+  uint32_t cr = (16384 << 16) | (1 << 3) | 1;
   tb->write(0x4, cr);
 
   //=================================
@@ -514,53 +443,38 @@ void tb_ecap5_dwbuart_read_rxdr(TB_Ecap5_dwbuart * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (4-7)
-  
-  tb->n_tick(4);
+  tb->write(0xC, 0xA5FA5FA5);
 
   //=================================
-  //      Tick (8-39)
+  //      Tick (4)
   
-  uint32_t data = 0x5F;
-  for(int i = 0; i < 8; i++) {
-    //`````````````````````````````````
-    //      Set inputs
-    
-    core->uart_rx_i = ((data >> i) & 0x1);
-
-    //=================================
-    //      Tick (...)
-    
-    tb->n_tick(4);
-  }
+  tb->tick();
 
   //`````````````````````````````````
   //      Set inputs
   
-  core->uart_rx_i = 1;
+  tb->_nop();
+  core->wb_cyc_i = 1;
 
   //=================================
-  //      Tick (40-43)
+  //      Tick (5)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Set inputs
   
-  core->uart_rx_i = 1;
-
-  //=================================
-  //      Tick (44-47)
-  
-  tb->n_tick(4);
+  tb->_nop();
+  core->wb_cyc_i = 0;
 
   //=================================
-  //      Tick (48)
+  //      Tick (6-50)
   
-  tb->tick();
+  // 1 start bit, 8 data bits, 1 parity bit, 0.5 stop bit
+  // the receive is valid at the half of the stop bit
+  uint32_t number_of_tx_bits = (1 + 8 + 1 + 1 + 0.5) * 4;
+  // This call is shifted by 1 tick from the emission start,
+  tb->n_tick(number_of_tx_bits - 1);
 
   //`````````````````````````````````
   //      Checks 
@@ -568,7 +482,7 @@ void tb_ecap5_dwbuart_read_rxdr(TB_Ecap5_dwbuart * tb) {
   tb->check(COND_rx, (core->tb_ecap5_dwbuart->dut->rx_valid == 1));
 
   //=================================
-  //      Tick (49)
+  //      Tick (51)
   
   tb->tick();
 
@@ -576,18 +490,19 @@ void tb_ecap5_dwbuart_read_rxdr(TB_Ecap5_dwbuart * tb) {
   //      Checks 
   
   tb->check(COND_rx, (core->tb_ecap5_dwbuart->dut->rx_valid == 0));
-  tb->check(COND_registers, (tb->uart_rxdr() == 0x5F) &&
+  tb->check(COND_registers, (tb->uart_rxdr() == 0xA5) &&
                             (tb->uart_sr() & 0x1));
 
   //=================================
-  //      Tick (50)
+  //      Tick (52)
   
+  core->probe = 0;
   tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_registers, (tb->uart_rxdr() == 0x5F) &&
+  tb->check(COND_registers, (tb->uart_rxdr() == 0xA5) &&
                             (tb->uart_sr() & 0x1));
 
   //`````````````````````````````````
@@ -596,14 +511,15 @@ void tb_ecap5_dwbuart_read_rxdr(TB_Ecap5_dwbuart * tb) {
   tb->read(0x8);
 
   //=================================
-  //      Tick (51)
+  //      Tick (53)
   
+  core->probe = 1;
   tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_mem, (core->tb_ecap5_dwbuart->dut->mem_read_data_q == 0x5F));
+  tb->check(COND_mem, (core->tb_ecap5_dwbuart->dut->mem_read_data_q == 0xA5));
   tb->check(COND_registers, (tb->uart_rxdr() == 0) &&
                             ((tb->uart_sr() & 0x1) == 0));
 
@@ -656,7 +572,8 @@ void tb_ecap5_dwbuart_rxoe(TB_Ecap5_dwbuart * tb) {
   //`````````````````````````````````
   //      Set inputs
 
-  uint32_t cr = (4 << 16) | (1 << 3) | 1;
+  // (2**16)/4 = 16384 = 1 bit every 4 clk cycles
+  uint32_t cr = (16384 << 16) | (1 << 3) | 1;
   tb->write(0x4, cr);
 
   //=================================
@@ -685,41 +602,79 @@ void tb_ecap5_dwbuart_rxoe(TB_Ecap5_dwbuart * tb) {
   
   tb->tick();
 
+  //`````````````````````````````````
+  //      Set inputs
+  
+  tb->write(0xC, 0xA5FA5FA5);
+
   //=================================
-  //      Tick (4-47)
+  //      Tick (4)
+  
+  tb->tick();
+
+  //`````````````````````````````````
+  //      Set inputs
   
-  tb->send(0x5F, 4, 1, 1, 0, 0, 0);
+  tb->_nop();
+  core->wb_cyc_i = 1;
 
   //=================================
-  //      Tick (48)
+  //      Tick (5)
   
   tb->tick();
 
+  //`````````````````````````````````
+  //      Set inputs
+  
+  tb->_nop();
+  core->wb_cyc_i = 0;
+
+  //=================================
+  //      Tick (6-50)
+  
+  // 1 start bit, 8 data bits, 1 parity bit, 0.5 stop bit
+  // the receive is valid at the half of the stop bit
+  uint32_t number_of_tx_bits = (1 + 8 + 1 + 1 + 0.5) * 4;
+  // This call is shifted by 1 tick from the emission start,
+  tb->n_tick(number_of_tx_bits - 1);
+
   //`````````````````````````````````
   //      Checks 
   
   tb->check(COND_rx, (core->tb_ecap5_dwbuart->dut->rx_valid == 1));
 
+  //`````````````````````````````````
+  //      Set inputs
+  
+  tb->write(0xC, 0xA5FAA5FA);
+
   //=================================
-  //      Tick (49)
+  //      Tick (51)
   
   tb->tick();
 
   //`````````````````````````````````
-  //      Checks 
+  //      Set inputs
   
-  tb->check(COND_rx, (core->tb_ecap5_dwbuart->dut->rx_valid == 0));
-  tb->check(COND_registers, (tb->uart_rxdr() == 0x5F));
+  tb->_nop();
+  core->wb_cyc_i = 1;
 
   //=================================
-  //      Tick (50-93)
+  //      Tick (52)
   
-  tb->send(0xF5, 4, 1, 1, 0, 0, 0);
+  tb->tick();
+
+  //`````````````````````````````````
+  //      Set inputs
+  
+  tb->_nop();
+  core->wb_cyc_i = 0;
 
   //=================================
-  //      Tick (94)
+  //      Tick (53-97)
   
-  tb->tick();
+  // This call is shifted by 1 tick from the emission start,
+  tb->n_tick(number_of_tx_bits - 1);
 
   //`````````````````````````````````
   //      Checks 
@@ -727,7 +682,7 @@ void tb_ecap5_dwbuart_rxoe(TB_Ecap5_dwbuart * tb) {
   tb->check(COND_rx, (core->tb_ecap5_dwbuart->dut->rx_valid == 1));
 
   //=================================
-  //      Tick (95)
+  //      Tick (98)
   
   tb->tick();
 
@@ -736,7 +691,7 @@ void tb_ecap5_dwbuart_rxoe(TB_Ecap5_dwbuart * tb) {
   
   tb->check(COND_rx, (core->tb_ecap5_dwbuart->dut->rx_valid == 0));
   tb->check(COND_registers, ((tb->uart_sr() >> 2) & 0x1) &&
-                             (tb->uart_rxdr() == 0xF5));
+                             (tb->uart_rxdr() == 0xFA));
 
   //`````````````````````````````````
   //      Set inputs
@@ -744,14 +699,14 @@ void tb_ecap5_dwbuart_rxoe(TB_Ecap5_dwbuart * tb) {
   tb->read(0x8);
 
   //=================================
-  //      Tick (96)
+  //      Tick (99)
   
   tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_mem, (core->tb_ecap5_dwbuart->dut->mem_read_data_q == 0xF5));
+  tb->check(COND_mem, (core->tb_ecap5_dwbuart->dut->mem_read_data_q == 0xFA));
   tb->check(COND_registers, ((tb->uart_sr() >> 2) & 0x1) &&
                              (tb->uart_rxdr() == 0x0));
 
@@ -762,7 +717,7 @@ void tb_ecap5_dwbuart_rxoe(TB_Ecap5_dwbuart * tb) {
   core->wb_cyc_i = 1;
 
   //=================================
-  //      Tick (97)
+  //      Tick (100)
   
   tb->tick();
 
@@ -772,7 +727,7 @@ void tb_ecap5_dwbuart_rxoe(TB_Ecap5_dwbuart * tb) {
   tb->_nop();
 
   //=================================
-  //      Tick (98)
+  //      Tick (101)
   
   tb->tick();
 
@@ -784,7 +739,7 @@ void tb_ecap5_dwbuart_rxoe(TB_Ecap5_dwbuart * tb) {
   uint32_t sr = tb->uart_sr();
 
   //=================================
-  //      Tick (99)
+  //      Tick (102)
   
   tb->tick();
 
@@ -801,7 +756,7 @@ void tb_ecap5_dwbuart_rxoe(TB_Ecap5_dwbuart * tb) {
   core->wb_cyc_i = 1;
 
   //=================================
-  //      Tick (100)
+  //      Tick (103)
   
   tb->tick();
 
@@ -811,7 +766,7 @@ void tb_ecap5_dwbuart_rxoe(TB_Ecap5_dwbuart * tb) {
   tb->_nop();
 
   //=================================
-  //      Tick (101)
+  //      Tick (104)
   
   tb->tick();
 
@@ -831,9 +786,9 @@ void tb_ecap5_dwbuart_rxoe(TB_Ecap5_dwbuart * tb) {
       "Failed to implement the memory-mapped registers", tb->err_cycles[COND_registers]);
 }
 
-void tb_ecap5_dwbuart_pe(TB_Ecap5_dwbuart * tb) {
+void tb_ecap5_dwbuart_fe(TB_Ecap5_dwbuart * tb) {
   Vtb_ecap5_dwbuart * core = tb->core;
-  core->testcase = T_PE;
+  core->testcase = T_FE;
 
   //=================================
   //      Tick (0)
@@ -843,7 +798,8 @@ void tb_ecap5_dwbuart_pe(TB_Ecap5_dwbuart * tb) {
   //`````````````````````````````````
   //      Set inputs
 
-  uint32_t cr = (4 << 16) | (1 << 3) | 1;
+  // (2**16)/4 = 16384 = 1 bit every 4 clk cycles
+  uint32_t cr = (16384 << 16) | (1 << 3) | 1;
   tb->write(0x4, cr);
 
   //=================================
@@ -872,20 +828,60 @@ void tb_ecap5_dwbuart_pe(TB_Ecap5_dwbuart * tb) {
   
   tb->tick();
 
+  //`````````````````````````````````
+  //      Set inputs
+  
+  tb->write(0xC, 0xA5FA5FA5);
+
   //=================================
-  //      Tick (4-47)
+  //      Tick (4)
+  
+  tb->tick();
+
+  //`````````````````````````````````
+  //      Set inputs
   
-  tb->send(0x5F, 4, 1, 1, 0, 1, 0);
+  tb->_nop();
+  core->wb_cyc_i = 1;
+
+  //=================================
+  //      Tick (5)
+  
+  tb->tick();
+
+  //`````````````````````````````````
+  //      Set inputs
+  
+  tb->_nop();
+  core->wb_cyc_i = 0;
 
   //=================================
-  //      Tick (48)
+  //      Tick (6-45)
   
-  tb->n_tick(2);
+  // 1 start bit, 8 data bits, 1 parity bit
+  // the receive is valid at the half of the stop bit
+  uint32_t number_of_tx_bits = (1 + 8 + 1 + 1) * 4;
+  // This call is shifted by 1 tick from the emission start
+  // and we want to be before the sending of the stop bit (3 cycles in advance)
+  tb->n_tick(number_of_tx_bits - 1 - 3);
+
+  //=================================
+  //      Tick (46-50)
+
+  // Inject the frame error
+  core->inj_frame_error = 1;
+  tb->n_tick(3 + 2);
+  core->inj_frame_error = 0;
+
+  //=================================
+  //      Tick (51)
+
+  tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_registers, (tb->uart_sr() >> 4) & 0x1);
+  tb->check(COND_registers, (tb->uart_sr() >> 3) & 0x1);
 
   //`````````````````````````````````
   //      Set inputs
@@ -903,7 +899,7 @@ void tb_ecap5_dwbuart_pe(TB_Ecap5_dwbuart * tb) {
   //      Checks 
   
   tb->check(COND_mem, (core->tb_ecap5_dwbuart->dut->mem_read_data_q == sr));
-  tb->check(COND_registers, (((tb->uart_sr() >> 4) & 0x1) == 0));
+  tb->check(COND_registers, (((tb->uart_sr() >> 3) & 0x1) == 0));
 
   //`````````````````````````````````
   //      Set inputs
@@ -929,18 +925,18 @@ void tb_ecap5_dwbuart_pe(TB_Ecap5_dwbuart * tb) {
   //`````````````````````````````````
   //      Formal Checks 
   
-  CHECK("tb_ecap5_dwbuart.pe.01",
+  CHECK("tb_ecap5_dwbuart.fe.01",
       tb->conditions[COND_mem],
       "Failed to integrate the memory", tb->err_cycles[COND_mem]);
 
-  CHECK("tb_ecap5_dwbuart.pe.02",
+  CHECK("tb_ecap5_dwbuart.fe.02",
       tb->conditions[COND_registers],
       "Failed to implement the memory-mapped registers", tb->err_cycles[COND_registers]);
 }
 
-void tb_ecap5_dwbuart_fe(TB_Ecap5_dwbuart * tb) {
+void tb_ecap5_dwbuart_pe(TB_Ecap5_dwbuart * tb) {
   Vtb_ecap5_dwbuart * core = tb->core;
-  core->testcase = T_FE;
+  core->testcase = T_PE;
 
   //=================================
   //      Tick (0)
@@ -950,7 +946,8 @@ void tb_ecap5_dwbuart_fe(TB_Ecap5_dwbuart * tb) {
   //`````````````````````````````````
   //      Set inputs
 
-  uint32_t cr = (4 << 16) | (1 << 3);
+  // (2**16)/4 = 16384 = 1 bit every 4 clk cycles
+  uint32_t cr = (16384 << 16) | (1 << 3) | 1;
   tb->write(0x4, cr);
 
   //=================================
@@ -979,20 +976,61 @@ void tb_ecap5_dwbuart_fe(TB_Ecap5_dwbuart * tb) {
   
   tb->tick();
 
+  //`````````````````````````````````
+  //      Set inputs
+  
+  tb->write(0xC, 0xA5FA5FA5);
+
+  //=================================
+  //      Tick (4)
+  
+  tb->tick();
+
+  //`````````````````````````````````
+  //      Set inputs
+  
+  tb->_nop();
+  core->wb_cyc_i = 1;
+
   //=================================
-  //      Tick (4-47)
+  //      Tick (5)
   
-  tb->send(0x5F, 4, 1, 0, 0, 0, 1);
+  tb->tick();
+
+  //`````````````````````````````````
+  //      Set inputs
+  
+  tb->_nop();
+  core->wb_cyc_i = 0;
 
   //=================================
-  //      Tick (48)
+  //      Tick (6-45)
   
-  tb->n_tick(2);
+  // 1 start bit, 8 data bits 
+  uint32_t number_of_tx_bits = (1 + 8 + 1) * 4;
+  // This call is shifted by 1 tick from the emission start
+  // and we want to be before the sending of the parity bit (3 cycles in advance)
+  tb->n_tick(number_of_tx_bits - 1 - 3);
+
+  //=================================
+  //      Tick (46-50)
+
+  // Inject the frame error for 3/4 of a bit
+  core->inj_parity_error = 1;
+  tb->n_tick(3);
+  core->inj_parity_error = 0;
+
+  // Stop injecting and tick for 
+  //   - 1 cycle for 1/4 of the previous bit
+  //   - 2 cycles for half of the stop bit 
+  //   - 1 cycle delay before the register is updated
+  //   - 3 cycles delay due to the input registering
+  tb->n_tick(1 + 2 + 1 + 3);
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_registers, (tb->uart_sr() >> 3) & 0x1);
+  tb->check(COND_registers, (tb->uart_sr() >> 4) & 0x1);
 
   //`````````````````````````````````
   //      Set inputs
@@ -1036,11 +1074,11 @@ void tb_ecap5_dwbuart_fe(TB_Ecap5_dwbuart * tb) {
   //`````````````````````````````````
   //      Formal Checks 
   
-  CHECK("tb_ecap5_dwbuart.fe.01",
+  CHECK("tb_ecap5_dwbuart.pe.01",
       tb->conditions[COND_mem],
       "Failed to integrate the memory", tb->err_cycles[COND_mem]);
 
-  CHECK("tb_ecap5_dwbuart.fe.02",
+  CHECK("tb_ecap5_dwbuart.pe.02",
       tb->conditions[COND_registers],
       "Failed to implement the memory-mapped registers", tb->err_cycles[COND_registers]);
 }
@@ -1084,7 +1122,7 @@ void tb_ecap5_dwbuart_full_duplex(TB_Ecap5_dwbuart * tb) {
   //=================================
   //      tick (3-46)
   
-  tb->send(0xFF, 4, 1, 0, 1, 0, 0);
+//  tb->send(0xFF, 4, 1, 0, 1, 0, 0);
 
   //=================================
   //      tick (47)
@@ -1107,7 +1145,7 @@ void tb_ecap5_dwbuart_full_duplex(TB_Ecap5_dwbuart * tb) {
   tb->_nop();
   core->wb_cyc_i = 1;
 
-  core->uart_rx_i = 0;
+//  core->uart_rx_i = 0;
 
   //=================================
   //      tick (49)
@@ -1132,7 +1170,7 @@ void tb_ecap5_dwbuart_full_duplex(TB_Ecap5_dwbuart * tb) {
     //`````````````````````````````````
     //      Set inputs
     
-    core->uart_rx_i = ((data >> i) & 0x1);
+    //core->uart_rx_i = ((data >> i) & 0x1);
 
     //=================================
     //      Tick (...)
@@ -1143,7 +1181,7 @@ void tb_ecap5_dwbuart_full_duplex(TB_Ecap5_dwbuart * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->uart_rx_i = 0;
+  //core->uart_rx_i = 0;
 
   //=================================
   //      Tick (85-88)
@@ -1153,7 +1191,7 @@ void tb_ecap5_dwbuart_full_duplex(TB_Ecap5_dwbuart * tb) {
   //`````````````````````````````````
   //      Set inputs
   
-  core->uart_rx_i = 0;
+  //core->uart_rx_i = 0;
 
   //=================================
   //      Tick (89-92)
@@ -1204,6 +1242,7 @@ int main(int argc, char ** argv, char ** env) {
   Verilated::traceEverOn(true);
 
   bool verbose = parse_verbose(argc, argv);
+  verbose = 1;
 
   TB_Ecap5_dwbuart * tb = new TB_Ecap5_dwbuart;
   tb->open_trace("waves/ecap5_dwbuart.vcd");
diff --git a/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.sv b/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.sv
index 4cad746..af062e5 100644
--- a/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.sv
+++ b/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.sv
@@ -43,10 +43,15 @@ module tb_ecap5_dwbuart
   //=================================
   //    Serial interface
   
-  input  logic uart_rx_i,
-  output logic uart_tx_o
+  output logic uart_tx_o,
+  input logic inj_frame_error,
+  input logic inj_parity_error,
+  input logic probe
 );
 
+logic uart_tx;
+logic uart_rx;
+
 ecap5_dwbuart dut (
   .clk_i           (clk_i),
   .rst_i           (rst_i),
@@ -61,10 +66,13 @@ ecap5_dwbuart dut (
   .wb_cyc_i   (wb_cyc_i),
   .wb_stall_o (wb_stall_o),
 
-  .uart_rx_i       (uart_rx_i),
-  .uart_tx_o       (uart_tx_o)
+  .uart_rx_i       (uart_rx),
+  .uart_tx_o       (uart_tx)
 );
 
+assign uart_tx_o = uart_tx;
+assign uart_rx = ~inj_frame_error & uart_tx ^ inj_parity_error;
+
 endmodule // tb_ecap5_dwbuart
 
 `verilator_config

From f0227a2e6adb13a1e6480d2abd931d0016850c01 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Cl=C3=A9ment=20Chaine?= <clement.chaine25@gmail.com>
Date: Fri, 5 Dec 2025 21:35:21 +0100
Subject: [PATCH 08/15] Update top module unit tests

---
 config/gtkwave/config/wb_interface.gtkw       |  67 --
 .../filters/ecap5_wbuart_testcase_filter.gtkw |   5 +-
 .../filters/wb_interface_testcase_filter.gtkw |   2 -
 .../ecap5_dwbuart/tb_ecap5_dwbuart.cpp        | 707 +++++++++---------
 tests/benches/rx_frontend/tb_rx_frontend.cpp  |   1 -
 5 files changed, 378 insertions(+), 404 deletions(-)
 delete mode 100644 config/gtkwave/config/wb_interface.gtkw
 delete mode 100644 config/gtkwave/filters/wb_interface_testcase_filter.gtkw

diff --git a/config/gtkwave/config/wb_interface.gtkw b/config/gtkwave/config/wb_interface.gtkw
deleted file mode 100644
index 241afb9..0000000
--- a/config/gtkwave/config/wb_interface.gtkw
+++ /dev/null
@@ -1,67 +0,0 @@
-[*]
-[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
-[*] Mon May  6 19:04:02 2024
-[*]
-[dumpfile] "/Users/cchaine/Desktop/Documents/projects/.ecap5.nosync/design/wbuart/build/tests/waves/wb_interface.vcd"
-[dumpfile_mtime] "Mon May  6 19:01:33 2024"
-[dumpfile_size] 3303
-[savefile] "/Users/cchaine/Desktop/Documents/projects/.ecap5.nosync/design/wbuart/config/gtkwave/config/wb_interface.gtkw"
-[timestart] 1
-[size] 1440 783
-[pos] -1 -1
-*-4.879648 -1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-[treeopen] TOP.
-[treeopen] TOP.tb_wb_interface.
-[sst_width] 253
-[signals_width] 177
-[sst_expanded] 1
-[sst_vpaned_height] 209
-@24
-[color] 1
-TOP.tb_wb_interface.testcase[31:0]
-@28
-TOP.tb_wb_interface.clk_i
-TOP.tb_wb_interface.rst_i
-@800200
--Wishbone
-@22
-[color] 2
-TOP.tb_wb_interface.wb_adr_i[31:0]
-[color] 2
-TOP.tb_wb_interface.wb_dat_i[31:0]
-[color] 2
-TOP.tb_wb_interface.wb_dat_o[31:0]
-@28
-[color] 2
-TOP.tb_wb_interface.wb_we_i
-@22
-[color] 2
-TOP.tb_wb_interface.wb_sel_i[3:0]
-@28
-[color] 2
-TOP.tb_wb_interface.wb_stb_i
-[color] 2
-TOP.tb_wb_interface.wb_ack_o
-[color] 2
-TOP.tb_wb_interface.wb_cyc_i
-[color] 2
-TOP.tb_wb_interface.wb_stall_o
-@1000200
--Wishbone
-@22
-[color] 7
-TOP.tb_wb_interface.addr_o[7:0]
-@28
-[color] 7
-TOP.tb_wb_interface.read_o
-@22
-[color] 7
-TOP.tb_wb_interface.read_data_i[31:0]
-@28
-[color] 7
-TOP.tb_wb_interface.write_o
-@22
-[color] 7
-TOP.tb_wb_interface.write_data_o[31:0]
-[pattern_trace] 1
-[pattern_trace] 0
diff --git a/config/gtkwave/filters/ecap5_wbuart_testcase_filter.gtkw b/config/gtkwave/filters/ecap5_wbuart_testcase_filter.gtkw
index e2149ec..d58fefb 100644
--- a/config/gtkwave/filters/ecap5_wbuart_testcase_filter.gtkw
+++ b/config/gtkwave/filters/ecap5_wbuart_testcase_filter.gtkw
@@ -5,4 +5,7 @@
 5 T_RXOE
 6 T_FE
 7 T_PE
-8 T_FULL_DUPLEX
+8 T_RACE_SR
+9 T_RACE_TXDR
+10 T_RACE_RXDR
+11 T_ERROR_RETENTION
diff --git a/config/gtkwave/filters/wb_interface_testcase_filter.gtkw b/config/gtkwave/filters/wb_interface_testcase_filter.gtkw
deleted file mode 100644
index 4f47d58..0000000
--- a/config/gtkwave/filters/wb_interface_testcase_filter.gtkw
+++ /dev/null
@@ -1,2 +0,0 @@
-1 T_READ
-2 T_WRITE
diff --git a/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.cpp b/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.cpp
index 6a99997..fd1b6a0 100644
--- a/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.cpp
+++ b/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.cpp
@@ -49,7 +49,10 @@ enum TestcaseId {
   T_RXOE                  = 5,
   T_FE                    = 6,
   T_PE                    = 7,
-  T_FULL_DUPLEX           = 8
+  T_RACE_SR               = 8,
+  T_RACE_TXDR             = 9,
+  T_RACE_RXDR             = 10,
+  T_ERROR_RETENTION       = 11
 };
 
 enum StateId {
@@ -77,7 +80,6 @@ class TB_Ecap5_dwbuart : public Testbench<Vtb_ecap5_dwbuart> {
     this->core->wb_stb_i = 0;
     this->core->wb_cyc_i = 0;
 
-//    this->core->uart_rx_i = 1;
   }
 
   void read(uint32_t addr) {
@@ -124,6 +126,162 @@ class TB_Ecap5_dwbuart : public Testbench<Vtb_ecap5_dwbuart> {
   uint32_t uart_txdr() {
     return core->tb_ecap5_dwbuart->dut->txdr_txd_q;
   }
+
+  void generate_read() {
+    // (2**16)/4 = 16384 = 1 bit every 4 clk cycles
+    uint32_t cr = (16384 << 16) | (1 << 3) | 1;
+    this->write(0x4, cr);
+    this->tick();
+
+    this->_nop();
+    this->core->wb_cyc_i = 1;
+    this->tick();
+
+    this->_nop();
+    this->tick();
+
+    this->write(0xC, 0xA5FA5FA5);
+    this->tick();
+
+    this->_nop();
+    this->core->wb_cyc_i = 1;
+    this->tick();
+
+    this->_nop();
+    this->core->wb_cyc_i = 0;
+    // 1 start bit, 8 data bits, 1 parity bit, 0.5 stop bit
+    // the receive is valid at the half of the stop bit
+    uint32_t number_of_tx_bits = (1 + 8 + 1 + 1 + 0.5) * 4;
+    // This call is shifted by 1 tick from the emission start,
+    // and this function shall put its caller the cycle before the valid signal is asserted
+    this->n_tick(number_of_tx_bits - 2);
+  }
+
+  void generate_fe() {
+    // (2**16)/4 = 16384 = 1 bit every 4 clk cycles
+    uint32_t cr = (16384 << 16) | (1 << 3) | 1;
+    this->write(0x4, cr);
+
+    this->tick();
+
+    this->_nop();
+    this->core->wb_cyc_i = 1;
+
+    this->tick();
+
+    this->_nop();
+
+    this->tick();
+
+    // Send the write data
+    this->write(0xC, 0xA5FA5FA5);
+
+    this->tick();
+
+    this->_nop();
+    this->core->wb_cyc_i = 1;
+
+    this->tick();
+
+    this->_nop();
+    this->core->wb_cyc_i = 0;
+
+    // 1 start bit, 8 data bits, 1 parity bit
+    // the receive is valid at the half of the stop bit
+    uint32_t number_of_tx_bits = (1 + 8 + 1 + 1) * 4;
+    // This call is shifted by 1 tick from the emission start
+    // and we want to be before the sending of the stop bit (3 cycles in advance)
+    this->n_tick(number_of_tx_bits - 1 - 3);
+
+    // Inject the frame error
+    this->core->inj_frame_error = 1;
+    this->n_tick(3 + 2);
+    this->core->inj_frame_error = 0;
+  }
+
+  void generate_pe() {
+    // (2**16)/4 = 16384 = 1 bit every 4 clk cycles
+    uint32_t cr = (16384 << 16) | (1 << 3) | 1;
+    this->write(0x4, cr);
+
+    this->tick();
+
+    this->_nop();
+    this->core->wb_cyc_i = 1;
+    this->tick();
+
+    this->_nop();
+    this->tick();
+
+    this->write(0xC, 0xA5FA5FA5);
+    this->tick();
+
+    this->_nop();
+    this->core->wb_cyc_i = 1;
+    this->tick();
+
+    this->_nop();
+    this->core->wb_cyc_i = 0;
+
+    // 1 start bit, 8 data bits 
+    uint32_t number_of_tx_bits = (1 + 8 + 1) * 4;
+    // This call is shifted by 1 tick from the emission start
+    // and we want to be before the sending of the parity bit (3 cycles in advance)
+    this->n_tick(number_of_tx_bits - 1 - 3);
+
+    // Inject the frame error for 3/4 of a bit
+    this->core->inj_parity_error = 1;
+    this->n_tick(3);
+    this->core->inj_parity_error = 0;
+
+    // Stop injecting and tick for 
+    //   - 1 cycle for 1/4 of the previous bit
+    //   - 2 cycles for half of the stop bit 
+    //   - 3 cycles delay due to the input registering
+    this->n_tick(1 + 2 + 3);
+  }
+
+  void generate_rxoe() {
+    // (2**16)/4 = 16384 = 1 bit every 4 clk cycles
+    uint32_t cr = (16384 << 16) | (1 << 3) | 1;
+    this->write(0x4, cr);
+
+    this->tick();
+
+    this->_nop();
+    this->core->wb_cyc_i = 1;
+    this->tick();
+
+    this->_nop();
+    this->tick();
+
+    this->write(0xC, 0xA5FA5FA5);
+    this->tick();
+
+    this->_nop();
+    this->core->wb_cyc_i = 1;
+    this->tick();
+
+    this->_nop();
+    this->core->wb_cyc_i = 0;
+    // 1 start bit, 8 data bits, 1 parity bit, 0.5 stop bit
+    // the receive is valid at the half of the stop bit
+    uint32_t number_of_tx_bits = (1 + 8 + 1 + 1 + 0.5) * 4;
+    // This call is shifted by 1 tick from the emission start,
+    this->n_tick(number_of_tx_bits - 1);
+
+    this->write(0xC, 0xA5FAA5FA);
+    this->tick();
+
+    this->_nop();
+    this->core->wb_cyc_i = 1;
+    this->tick();
+
+    this->_nop();
+    this->core->wb_cyc_i = 0;
+    // and this function shall put its caller the cycle before the valid signal is asserted
+    this->n_tick(number_of_tx_bits - 2);
+  }
 };
 
 void tb_ecap5_dwbuart_idle(TB_Ecap5_dwbuart * tb) {
@@ -407,75 +565,16 @@ void tb_ecap5_dwbuart_read_rxdr(TB_Ecap5_dwbuart * tb) {
   
   tb->reset();
 
-  //`````````````````````````````````
-  //      Set inputs
-
-  // (2**16)/4 = 16384 = 1 bit every 4 clk cycles
-  uint32_t cr = (16384 << 16) | (1 << 3) | 1;
-  tb->write(0x4, cr);
-
   //=================================
-  //      Tick (1)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  tb->_nop();
-  core->wb_cyc_i = 1;
-
-  //=================================
-  //      Tick (2)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  tb->_nop();
-
-  //=================================
-  //      Tick (3)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  tb->write(0xC, 0xA5FA5FA5);
-
-  //=================================
-  //      Tick (4)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
+  //      Tick (1-49)
   
-  tb->_nop();
-  core->wb_cyc_i = 1;
+  tb->generate_read();
 
   //=================================
-  //      Tick (5)
+  //      Tick (50)
   
   tb->tick();
 
-  //`````````````````````````````````
-  //      Set inputs
-  
-  tb->_nop();
-  core->wb_cyc_i = 0;
-
-  //=================================
-  //      Tick (6-50)
-  
-  // 1 start bit, 8 data bits, 1 parity bit, 0.5 stop bit
-  // the receive is valid at the half of the stop bit
-  uint32_t number_of_tx_bits = (1 + 8 + 1 + 1 + 0.5) * 4;
-  // This call is shifted by 1 tick from the emission start,
-  tb->n_tick(number_of_tx_bits - 1);
-
   //`````````````````````````````````
   //      Checks 
   
@@ -496,7 +595,6 @@ void tb_ecap5_dwbuart_read_rxdr(TB_Ecap5_dwbuart * tb) {
   //=================================
   //      Tick (52)
   
-  core->probe = 0;
   tb->tick();
 
   //`````````````````````````````````
@@ -513,7 +611,6 @@ void tb_ecap5_dwbuart_read_rxdr(TB_Ecap5_dwbuart * tb) {
   //=================================
   //      Tick (53)
   
-  core->probe = 1;
   tb->tick();
 
   //`````````````````````````````````
@@ -569,113 +666,16 @@ void tb_ecap5_dwbuart_rxoe(TB_Ecap5_dwbuart * tb) {
   
   tb->reset();
 
-  //`````````````````````````````````
-  //      Set inputs
-
-  // (2**16)/4 = 16384 = 1 bit every 4 clk cycles
-  uint32_t cr = (16384 << 16) | (1 << 3) | 1;
-  tb->write(0x4, cr);
-
-  //=================================
-  //      Tick (1)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  tb->_nop();
-  core->wb_cyc_i = 1;
-
   //=================================
-  //      Tick (2)
+  //      Tick (1-96)
   
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  tb->_nop();
+  tb->generate_rxoe();
 
   //=================================
-  //      Tick (3)
+  //      Tick (97)
   
   tb->tick();
 
-  //`````````````````````````````````
-  //      Set inputs
-  
-  tb->write(0xC, 0xA5FA5FA5);
-
-  //=================================
-  //      Tick (4)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  tb->_nop();
-  core->wb_cyc_i = 1;
-
-  //=================================
-  //      Tick (5)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  tb->_nop();
-  core->wb_cyc_i = 0;
-
-  //=================================
-  //      Tick (6-50)
-  
-  // 1 start bit, 8 data bits, 1 parity bit, 0.5 stop bit
-  // the receive is valid at the half of the stop bit
-  uint32_t number_of_tx_bits = (1 + 8 + 1 + 1 + 0.5) * 4;
-  // This call is shifted by 1 tick from the emission start,
-  tb->n_tick(number_of_tx_bits - 1);
-
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_rx, (core->tb_ecap5_dwbuart->dut->rx_valid == 1));
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  tb->write(0xC, 0xA5FAA5FA);
-
-  //=================================
-  //      Tick (51)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  tb->_nop();
-  core->wb_cyc_i = 1;
-
-  //=================================
-  //      Tick (52)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
-  
-  tb->_nop();
-  core->wb_cyc_i = 0;
-
-  //=================================
-  //      Tick (53-97)
-  
-  // This call is shifted by 1 tick from the emission start,
-  tb->n_tick(number_of_tx_bits - 1);
-
   //`````````````````````````````````
   //      Checks 
   
@@ -795,48 +795,33 @@ void tb_ecap5_dwbuart_fe(TB_Ecap5_dwbuart * tb) {
   
   tb->reset();
 
-  //`````````````````````````````````
-  //      Set inputs
-
-  // (2**16)/4 = 16384 = 1 bit every 4 clk cycles
-  uint32_t cr = (16384 << 16) | (1 << 3) | 1;
-  tb->write(0x4, cr);
-
   //=================================
-  //      Tick (1)
-  
-  tb->tick();
-
-  //`````````````````````````````````
-  //      Set inputs
+  //      Tick (1-47)
   
-  tb->_nop();
-  core->wb_cyc_i = 1;
+  tb->generate_fe();
 
   //=================================
-  //      Tick (2)
+  //      Tick (48)
   
   tb->tick();
 
   //`````````````````````````````````
   //      Set inputs
-  
-  tb->_nop();
+
+  tb->read(0x0);
+
+  uint32_t sr = tb->uart_sr();
 
   //=================================
-  //      Tick (3)
+  //      Tick (49)
   
   tb->tick();
 
   //`````````````````````````````````
-  //      Set inputs
-  
-  tb->write(0xC, 0xA5FA5FA5);
-
-  //=================================
-  //      Tick (4)
+  //      Checks 
   
-  tb->tick();
+  tb->check(COND_mem, (core->tb_ecap5_dwbuart->dut->mem_read_data_q == sr));
+  tb->check(COND_registers, (((tb->uart_sr() >> 3) & 0x1) == 0));
 
   //`````````````````````````````````
   //      Set inputs
@@ -845,7 +830,7 @@ void tb_ecap5_dwbuart_fe(TB_Ecap5_dwbuart * tb) {
   core->wb_cyc_i = 1;
 
   //=================================
-  //      Tick (5)
+  //      Tick (50)
   
   tb->tick();
 
@@ -853,35 +838,37 @@ void tb_ecap5_dwbuart_fe(TB_Ecap5_dwbuart * tb) {
   //      Set inputs
   
   tb->_nop();
-  core->wb_cyc_i = 0;
 
   //=================================
-  //      Tick (6-45)
+  //      Tick (51)
   
-  // 1 start bit, 8 data bits, 1 parity bit
-  // the receive is valid at the half of the stop bit
-  uint32_t number_of_tx_bits = (1 + 8 + 1 + 1) * 4;
-  // This call is shifted by 1 tick from the emission start
-  // and we want to be before the sending of the stop bit (3 cycles in advance)
-  tb->n_tick(number_of_tx_bits - 1 - 3);
+  tb->tick();
 
-  //=================================
-  //      Tick (46-50)
+  //`````````````````````````````````
+  //      Formal Checks 
+  
+  CHECK("tb_ecap5_dwbuart.fe.01",
+      tb->conditions[COND_mem],
+      "Failed to integrate the memory", tb->err_cycles[COND_mem]);
 
-  // Inject the frame error
-  core->inj_frame_error = 1;
-  tb->n_tick(3 + 2);
-  core->inj_frame_error = 0;
+  CHECK("tb_ecap5_dwbuart.fe.02",
+      tb->conditions[COND_registers],
+      "Failed to implement the memory-mapped registers", tb->err_cycles[COND_registers]);
+}
 
-  //=================================
-  //      Tick (51)
+void tb_ecap5_dwbuart_pe(TB_Ecap5_dwbuart * tb) {
+  Vtb_ecap5_dwbuart * core = tb->core;
+  core->testcase = T_PE;
 
-  tb->tick();
+  //=================================
+  //      Tick (0)
+  
+  tb->reset();
 
-  //`````````````````````````````````
-  //      Checks 
+  //=================================
+  //      Tick (1-47)
   
-  tb->check(COND_registers, (tb->uart_sr() >> 3) & 0x1);
+  tb->generate_pe();
 
   //`````````````````````````````````
   //      Set inputs
@@ -925,36 +912,69 @@ void tb_ecap5_dwbuart_fe(TB_Ecap5_dwbuart * tb) {
   //`````````````````````````````````
   //      Formal Checks 
   
-  CHECK("tb_ecap5_dwbuart.fe.01",
+  CHECK("tb_ecap5_dwbuart.pe.01",
       tb->conditions[COND_mem],
       "Failed to integrate the memory", tb->err_cycles[COND_mem]);
 
-  CHECK("tb_ecap5_dwbuart.fe.02",
+  CHECK("tb_ecap5_dwbuart.pe.02",
       tb->conditions[COND_registers],
       "Failed to implement the memory-mapped registers", tb->err_cycles[COND_registers]);
 }
 
-void tb_ecap5_dwbuart_pe(TB_Ecap5_dwbuart * tb) {
+/**
+ * @brief Generate all possible errors one by one and then
+ *        generate a successfull read.
+ *        The errors are expected to have accumulated.
+ */
+void tb_ecap5_dwbuart_error_retention(TB_Ecap5_dwbuart * tb) {
   Vtb_ecap5_dwbuart * core = tb->core;
-  core->testcase = T_PE;
+  core->testcase = T_ERROR_RETENTION;
 
   //=================================
   //      Tick (0)
   
   tb->reset();
 
+  // Generate the three errors
+  tb->generate_rxoe();
+  tb->tick();
+  tb->generate_fe();
+  tb->tick();
+  tb->generate_pe();
+  tb->tick();
+
+  // Send a clean frame
+  tb->generate_read();
+  tb->tick();
+
+  //=================================
+  //      Tick (250)
+
+  tb->tick();
+  
   //`````````````````````````````````
-  //      Set inputs
+  //      Checks 
+  
+  // Check that every errors is still present
+  tb->check(COND_registers, ((tb->uart_sr() >> 2) & 0x7) == 0x7);
 
-  // (2**16)/4 = 16384 = 1 bit every 4 clk cycles
-  uint32_t cr = (16384 << 16) | (1 << 3) | 1;
-  tb->write(0x4, cr);
+  //`````````````````````````````````
+  //      Set inputs
+  
+  tb->read(0x0);
+  uint32_t sr = tb->uart_sr();
 
   //=================================
-  //      Tick (1)
+  //      Tick (251)
   
   tb->tick();
 
+  //`````````````````````````````````
+  //      Checks 
+  
+  tb->check(COND_mem, (core->tb_ecap5_dwbuart->dut->mem_read_data_q == sr));
+  tb->check(COND_registers, (((tb->uart_sr() >> 2) & 0x7) == 0));
+
   //`````````````````````````````````
   //      Set inputs
   
@@ -962,7 +982,7 @@ void tb_ecap5_dwbuart_pe(TB_Ecap5_dwbuart * tb) {
   core->wb_cyc_i = 1;
 
   //=================================
-  //      Tick (2)
+  //      Tick (252)
   
   tb->tick();
 
@@ -972,20 +992,53 @@ void tb_ecap5_dwbuart_pe(TB_Ecap5_dwbuart * tb) {
   tb->_nop();
 
   //=================================
-  //      Tick (3)
+  //      Tick (253)
   
   tb->tick();
 
   //`````````````````````````````````
-  //      Set inputs
+  //      Formal Checks 
+
+  CHECK("tb_ecap5_dwbuart.error_retention.01",
+      tb->conditions[COND_mem],
+      "Failed to integrate the memory", tb->err_cycles[COND_mem]);
+
+  CHECK("tb_ecap5_dwbuart.error_retention.02",
+      tb->conditions[COND_registers],
+      "Failed to implement the memory-mapped registers", tb->err_cycles[COND_registers]);
+}
+
+/**
+ * @brief Read SR at the same time as status bits are written to it
+ *        Instead of reseting SR after reading, the bits are properly written
+ */
+void tb_ecap5_dwbuart_race_sr(TB_Ecap5_dwbuart * tb) {
+  Vtb_ecap5_dwbuart * core = tb->core;
+  core->testcase = T_RACE_SR;
+
+  //=================================
+  //      Tick (0)
   
-  tb->write(0xC, 0xA5FA5FA5);
+  tb->reset();
+
+  tb->generate_pe();
+
+  //`````````````````````````````````
+  //      Set inputs
+
+  tb->read(0x0);
 
   //=================================
-  //      Tick (4)
+  //      Tick (50)
   
   tb->tick();
 
+  //`````````````````````````````````
+  //      Checks 
+  
+  tb->check(COND_mem, ((core->tb_ecap5_dwbuart->dut->mem_read_data_q >> 4) & 0x1) == 0);
+  tb->check(COND_registers, (((tb->uart_sr() >> 4) & 0x1) == 1));
+
   //`````````````````````````````````
   //      Set inputs
   
@@ -993,7 +1046,7 @@ void tb_ecap5_dwbuart_pe(TB_Ecap5_dwbuart * tb) {
   core->wb_cyc_i = 1;
 
   //=================================
-  //      Tick (5)
+  //      Tick (50)
   
   tb->tick();
 
@@ -1001,44 +1054,17 @@ void tb_ecap5_dwbuart_pe(TB_Ecap5_dwbuart * tb) {
   //      Set inputs
   
   tb->_nop();
-  core->wb_cyc_i = 0;
 
   //=================================
-  //      Tick (6-45)
+  //      Tick (51)
   
-  // 1 start bit, 8 data bits 
-  uint32_t number_of_tx_bits = (1 + 8 + 1) * 4;
-  // This call is shifted by 1 tick from the emission start
-  // and we want to be before the sending of the parity bit (3 cycles in advance)
-  tb->n_tick(number_of_tx_bits - 1 - 3);
-
-  //=================================
-  //      Tick (46-50)
-
-  // Inject the frame error for 3/4 of a bit
-  core->inj_parity_error = 1;
-  tb->n_tick(3);
-  core->inj_parity_error = 0;
-
-  // Stop injecting and tick for 
-  //   - 1 cycle for 1/4 of the previous bit
-  //   - 2 cycles for half of the stop bit 
-  //   - 1 cycle delay before the register is updated
-  //   - 3 cycles delay due to the input registering
-  tb->n_tick(1 + 2 + 1 + 3);
-
-  //`````````````````````````````````
-  //      Checks 
+  tb->tick();
   
-  tb->check(COND_registers, (tb->uart_sr() >> 4) & 0x1);
-
   //`````````````````````````````````
   //      Set inputs
 
   tb->read(0x0);
 
-  uint32_t sr = tb->uart_sr();
-
   //=================================
   //      Tick (49)
   
@@ -1047,8 +1073,8 @@ void tb_ecap5_dwbuart_pe(TB_Ecap5_dwbuart * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_mem, (core->tb_ecap5_dwbuart->dut->mem_read_data_q == sr));
-  tb->check(COND_registers, (((tb->uart_sr() >> 3) & 0x1) == 0));
+  tb->check(COND_mem, ((core->tb_ecap5_dwbuart->dut->mem_read_data_q >> 4) & 0x1) == 1);
+  tb->check(COND_registers, (((tb->uart_sr() >> 4) & 0x1) == 0));
 
   //`````````````````````````````````
   //      Set inputs
@@ -1074,165 +1100,178 @@ void tb_ecap5_dwbuart_pe(TB_Ecap5_dwbuart * tb) {
   //`````````````````````````````````
   //      Formal Checks 
   
-  CHECK("tb_ecap5_dwbuart.pe.01",
+  CHECK("tb_ecap5_dwbuart.race_sr.01",
       tb->conditions[COND_mem],
       "Failed to integrate the memory", tb->err_cycles[COND_mem]);
 
-  CHECK("tb_ecap5_dwbuart.pe.02",
+  CHECK("tb_ecap5_dwbuart.race_sr.02",
       tb->conditions[COND_registers],
       "Failed to implement the memory-mapped registers", tb->err_cycles[COND_registers]);
 }
 
-void tb_ecap5_dwbuart_full_duplex(TB_Ecap5_dwbuart * tb) {
+/**
+ * @brief Write to TXDR at the same time as the previous transfer is done
+ *        Instead of setting TXE, TXE shall stay low
+ */
+void tb_ecap5_dwbuart_race_txdr(TB_Ecap5_dwbuart * tb) {
   Vtb_ecap5_dwbuart * core = tb->core;
-  core->testcase = T_FULL_DUPLEX;
+  core->testcase = T_RACE_TXDR;
 
   //=================================
   //      Tick (0)
   
   tb->reset();
 
-  //`````````````````````````````````
-  //      set inputs
+  tb->generate_read();
 
-  uint32_t cr = (4 << 16) | (1 << 3) | 1;
-  tb->write(0x4, cr);
+  //`````````````````````````````````
+  //      Set inputs
+  
+  tb->write(0xC, 0xA5FA5FA5);
 
   //=================================
-  //      tick (1)
+  //      Tick (4)
   
   tb->tick();
 
   //`````````````````````````````````
-  //      set inputs
+  //      Checks 
+  
+  tb->check(COND_registers, ((tb->uart_sr() & 0x2) == 0));
+  tb->check(COND_registers, (tb->uart_txdr() == 0x000000A5));
+  tb->check(COND_tx,        (core->tb_ecap5_dwbuart->dut->tx_transmit_q == 1));
+
+  //`````````````````````````````````
+  //      Set inputs
   
   tb->_nop();
   core->wb_cyc_i = 1;
 
   //=================================
-  //      tick (2)
+  //      Tick (5)
   
   tb->tick();
 
   //`````````````````````````````````
-  //      set inputs
+  //      Set inputs
   
   tb->_nop();
+  core->wb_cyc_i = 0;
 
-  //=================================
-  //      tick (3-46)
-  
-//  tb->send(0xFF, 4, 1, 0, 1, 0, 0);
-
-  //=================================
-  //      tick (47)
-  
   tb->tick();
 
   //`````````````````````````````````
-  //      set inputs
+  //      Formal Checks 
+  
+  CHECK("tb_ecap5_dwbuart.race_txdr.01",
+      tb->conditions[COND_rx],
+      "Failed to integrate the rx frontend", tb->err_cycles[COND_rx]);
+
+  CHECK("tb_ecap5_dwbuart.race_txdr.02",
+      tb->conditions[COND_tx],
+      "Failed to integrate the tx frontend", tb->err_cycles[COND_tx]);
 
-  tb->write(0xC, 0xAF);
+  CHECK("tb_ecap5_dwbuart.race_txdr.03",
+      tb->conditions[COND_registers],
+      "Failed to implement the memory-mapped registers", tb->err_cycles[COND_registers]);
+}
+
+void tb_ecap5_dwbuart_race_rxdr(TB_Ecap5_dwbuart * tb) {
+  Vtb_ecap5_dwbuart * core = tb->core;
+  core->testcase = T_RACE_RXDR;
 
   //=================================
-  //      tick (48)
+  //      Tick (0)
   
+  tb->reset();
+
+  tb->generate_read();
+
   tb->tick();
 
   //`````````````````````````````````
-  //      set inputs
+  //      Set inputs
   
-  tb->_nop();
-  core->wb_cyc_i = 1;
-
-//  core->uart_rx_i = 0;
+  tb->read(0x8);
 
   //=================================
-  //      tick (49)
+  //      Tick (53)
   
   tb->tick();
 
   //`````````````````````````````````
-  //      set inputs
+  //      Checks 
   
-  core->wb_cyc_i = 0;
+  // Expected to be true even if a read was performed
+  tb->check(COND_registers, (tb->uart_sr() & 0x1) == 1);
 
-  //=================================
-  //      Tick (50-52)
+  //`````````````````````````````````
+  //      Set inputs
   
-  tb->n_tick(3);
+  tb->_nop();
+  core->wb_cyc_i = 1;
 
   //=================================
-  //      Tick (53-84)
+  //      Tick (52)
   
-  uint32_t data = 0x5F;
-  for(int i = 0; i < 8; i++) {
-    //`````````````````````````````````
-    //      Set inputs
-    
-    //core->uart_rx_i = ((data >> i) & 0x1);
-
-    //=================================
-    //      Tick (...)
-    
-    tb->n_tick(4);
-  }
+  tb->tick();
 
   //`````````````````````````````````
   //      Set inputs
   
-  //core->uart_rx_i = 0;
+  tb->_nop();
 
   //=================================
-  //      Tick (85-88)
+  //      Tick (53)
   
-  tb->n_tick(4);
+  tb->tick();
 
   //`````````````````````````````````
   //      Set inputs
   
-  //core->uart_rx_i = 0;
-
-  //=================================
-  //      Tick (89-92)
-  
-  tb->n_tick(4);
+  tb->read(0x8);
 
   //=================================
-  //      Tick (93)
+  //      Tick (53)
   
   tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_rx, (core->tb_ecap5_dwbuart->dut->rx_valid == 1));
-  tb->check(COND_tx, (core->tb_ecap5_dwbuart->dut->tx_done == 1));
+  tb->check(COND_mem, (core->tb_ecap5_dwbuart->dut->mem_read_data_q == 0xA5));
+  tb->check(COND_registers, (tb->uart_rxdr() == 0) &&
+                            ((tb->uart_sr() & 0x1) == 0));
+
+  //`````````````````````````````````
+  //      Set inputs
+  
+  tb->_nop();
+  core->wb_cyc_i = 1;
 
   //=================================
-  //      Tick (94)
+  //      Tick (52)
   
   tb->tick();
 
   //`````````````````````````````````
-  //      Checks 
+  //      Set inputs
   
-  tb->check(COND_rx, (core->tb_ecap5_dwbuart->dut->rx_valid == 0));
-  tb->check(COND_registers, (tb->uart_rxdr() == 0x5F) &&
-                            (tb->uart_sr() == 0x1F));
+  tb->_nop();
+
+  //=================================
+  //      Tick (53)
+  
+  tb->tick();
 
   //`````````````````````````````````
   //      Formal Checks 
   
-  CHECK("tb_ecap5_dwbuart.full_duplex.01",
-      tb->conditions[COND_rx],
-      "Failed to integrate the rx frontend", tb->err_cycles[COND_rx]);
-
-  CHECK("tb_ecap5_dwbuart.full_duplex.02",
-      tb->conditions[COND_tx],
-      "Failed to integrate the tx frontend", tb->err_cycles[COND_tx]);
+  CHECK("tb_ecap5_dwbuart.race_rxdr.01",
+      tb->conditions[COND_mem],
+      "Failed to integrate the memory", tb->err_cycles[COND_mem]);
 
-  CHECK("tb_ecap5_dwbuart.full_duplex.03",
+  CHECK("tb_ecap5_dwbuart.race_rxdr.02",
       tb->conditions[COND_registers],
       "Failed to implement the memory-mapped registers", tb->err_cycles[COND_registers]);
 }
@@ -1242,7 +1281,6 @@ int main(int argc, char ** argv, char ** env) {
   Verilated::traceEverOn(true);
 
   bool verbose = parse_verbose(argc, argv);
-  verbose = 1;
 
   TB_Ecap5_dwbuart * tb = new TB_Ecap5_dwbuart;
   tb->open_trace("waves/ecap5_dwbuart.vcd");
@@ -1262,7 +1300,10 @@ int main(int argc, char ** argv, char ** env) {
   tb_ecap5_dwbuart_fe(tb);
   tb_ecap5_dwbuart_pe(tb);
 
-  tb_ecap5_dwbuart_full_duplex(tb);
+  tb_ecap5_dwbuart_error_retention(tb);
+  tb_ecap5_dwbuart_race_sr(tb);
+  tb_ecap5_dwbuart_race_txdr(tb);
+  tb_ecap5_dwbuart_race_rxdr(tb);
 
   /************************************************************/
 
diff --git a/tests/benches/rx_frontend/tb_rx_frontend.cpp b/tests/benches/rx_frontend/tb_rx_frontend.cpp
index d706255..fcac3d1 100644
--- a/tests/benches/rx_frontend/tb_rx_frontend.cpp
+++ b/tests/benches/rx_frontend/tb_rx_frontend.cpp
@@ -954,7 +954,6 @@ int main(int argc, char ** argv, char ** env) {
   Verilated::traceEverOn(true);
 
   bool verbose = parse_verbose(argc, argv);
-  verbose = 1;
 
   TB_Rx_frontend * tb = new TB_Rx_frontend;
   tb->open_trace("waves/rx_frontend.vcd");

From f9d66c8a92623f360fa8de2a39870eed90628156 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Cl=C3=A9ment=20Chaine?= <clement.chaine25@gmail.com>
Date: Fri, 5 Dec 2025 22:24:45 +0100
Subject: [PATCH 09/15] Fix wrong baudrate in rx_frontend testsuite

---
 .../benches/ecap5_dwbuart/tb_ecap5_dwbuart.sv |  3 +-
 tests/benches/rx_frontend/tb_rx_frontend.cpp  | 34 ++++++++-----------
 tests/benches/rx_frontend/tb_rx_frontend.sv   |  3 +-
 3 files changed, 17 insertions(+), 23 deletions(-)

diff --git a/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.sv b/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.sv
index af062e5..089326d 100644
--- a/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.sv
+++ b/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.sv
@@ -45,8 +45,7 @@ module tb_ecap5_dwbuart
   
   output logic uart_tx_o,
   input logic inj_frame_error,
-  input logic inj_parity_error,
-  input logic probe
+  input logic inj_parity_error
 );
 
 logic uart_tx;
diff --git a/tests/benches/rx_frontend/tb_rx_frontend.cpp b/tests/benches/rx_frontend/tb_rx_frontend.cpp
index fcac3d1..208c00a 100644
--- a/tests/benches/rx_frontend/tb_rx_frontend.cpp
+++ b/tests/benches/rx_frontend/tb_rx_frontend.cpp
@@ -100,8 +100,6 @@ class TB_Rx_frontend : public Testbench<Vtb_rx_frontend> {
     core->cr_ds_i = 0;
     core->cr_p_i = 0;
     core->cr_s_i = 0;
-
-    core->test = 0;
   }
   
   void set_injected_baudrate(uint32_t acc_increment) {
@@ -183,14 +181,12 @@ class TB_Rx_frontend : public Testbench<Vtb_rx_frontend> {
     for(int i = 0; i < num_stop_bits; i++) {
       // If this is the last stop bit
       if(i == (num_stop_bits - 1)) {
-        this->core->test = 1;
         // Send half of the first cycle + 3 as the used signal is delayed by three
         // clock cycles. Ceil is as sometimes cycles to run is not equal to the first
         // cycle which created the sampling offset.
         // This is done in order to catch the tx_done signal
         cycles_to_run = get_cycles_before_next_accumulator_overflow();
         this->n_tick(sampling_offset + 3);
-        this->core->test = 0;
 
         // Check the result
         uint32_t stop_bits = config.s ? 3 : 1;
@@ -291,7 +287,7 @@ void tb_rx_frontend_valid_frame_7N1(TB_Rx_frontend * tb) {
   //      Checks 
   
   test_configuration_t config = {
-    .baudrate = 25000000,
+    .baudrate = 2500000,
     .data = 0b10100101,
     .ds = 0,
     .p = 0,
@@ -334,7 +330,7 @@ void tb_rx_frontend_valid_frame_7N2(TB_Rx_frontend * tb) {
   //      Checks 
   
   test_configuration_t config = {
-    .baudrate = 25000000,
+    .baudrate = 2500000,
     .data = 0b10100101,
     .ds = 0,
     .p = 0,
@@ -377,7 +373,7 @@ void tb_rx_frontend_valid_frame_7E1(TB_Rx_frontend * tb) {
   //      Checks 
   
   test_configuration_t config = {
-    .baudrate = 25000000,
+    .baudrate = 2500000,
     .data = 0b10100101,
     .ds = 0,
     .p = 2,
@@ -420,7 +416,7 @@ void tb_rx_frontend_valid_frame_7E2(TB_Rx_frontend * tb) {
   //      Checks 
   
   test_configuration_t config = {
-    .baudrate = 25000000,
+    .baudrate = 2500000,
     .data = 0b10100101,
     .ds = 0,
     .p = 2,
@@ -463,7 +459,7 @@ void tb_rx_frontend_valid_frame_7O1(TB_Rx_frontend * tb) {
   //      Checks 
   
   test_configuration_t config = {
-    .baudrate = 25000000,
+    .baudrate = 2500000,
     .data = 0b10100101,
     .ds = 0,
     .p = 1,
@@ -506,7 +502,7 @@ void tb_rx_frontend_valid_frame_7O2(TB_Rx_frontend * tb) {
   //      Checks 
   
   test_configuration_t config = {
-    .baudrate = 25000000,
+    .baudrate = 2500000,
     .data = 0b10100101,
     .ds = 0,
     .p = 1,
@@ -549,7 +545,7 @@ void tb_rx_frontend_valid_frame_8N1(TB_Rx_frontend * tb) {
   //      Checks 
   
   test_configuration_t config = {
-    .baudrate = 25000000,
+    .baudrate = 2500000,
     .data = 0b10100101,
     .ds = 1,
     .p = 0,
@@ -592,7 +588,7 @@ void tb_rx_frontend_valid_frame_8N2(TB_Rx_frontend * tb) {
   //      Checks 
   
   test_configuration_t config = {
-    .baudrate = 25000000,
+    .baudrate = 2500000,
     .data = 0b10100101,
     .ds = 1,
     .p = 0,
@@ -635,7 +631,7 @@ void tb_rx_frontend_valid_frame_8E1(TB_Rx_frontend * tb) {
   //      Checks 
   
   test_configuration_t config = {
-    .baudrate = 25000000,
+    .baudrate = 2500000,
     .data = 0b10100101,
     .ds = 1,
     .p = 2,
@@ -678,7 +674,7 @@ void tb_rx_frontend_valid_frame_8E2(TB_Rx_frontend * tb) {
   //      Checks 
   
   test_configuration_t config = {
-    .baudrate = 25000000,
+    .baudrate = 2500000,
     .data = 0b10100101,
     .ds = 1,
     .p = 2,
@@ -721,7 +717,7 @@ void tb_rx_frontend_valid_frame_8O1(TB_Rx_frontend * tb) {
   //      Checks 
   
   test_configuration_t config = {
-    .baudrate = 25000000,
+    .baudrate = 2500000,
     .data = 0b10100101,
     .ds = 1,
     .p = 1,
@@ -764,7 +760,7 @@ void tb_rx_frontend_valid_frame_8O2(TB_Rx_frontend * tb) {
   //      Checks 
   
   test_configuration_t config = {
-    .baudrate = 25000000,
+    .baudrate = 2500000,
     .data = 0b10100101,
     .ds = 1,
     .p = 1,
@@ -804,7 +800,7 @@ void tb_rx_frontend_parity_even(TB_Rx_frontend * tb) {
   tb->reset();
 
   test_configuration_t config = {
-    .baudrate = 25000000,
+    .baudrate = 2500000,
     .data = 0b10100101,
     .ds = 0,
     .p = 2,
@@ -836,7 +832,7 @@ void tb_rx_frontend_parity_odd(TB_Rx_frontend * tb) {
   tb->reset();
 
   test_configuration_t config = {
-    .baudrate = 25000000,
+    .baudrate = 2500000,
     .data = 0b10100101,
     .ds = 0,
     .p = 1,
@@ -868,7 +864,7 @@ void tb_rx_frontend_framing(TB_Rx_frontend * tb) {
   tb->reset();
 
   test_configuration_t config = {
-    .baudrate = 25000000,
+    .baudrate = 2500000,
     .data = 0b10100101,
     .ds = 0,
     .p = 0,
diff --git a/tests/benches/rx_frontend/tb_rx_frontend.sv b/tests/benches/rx_frontend/tb_rx_frontend.sv
index d366dbd..69cc99f 100644
--- a/tests/benches/rx_frontend/tb_rx_frontend.sv
+++ b/tests/benches/rx_frontend/tb_rx_frontend.sv
@@ -37,8 +37,7 @@ module tb_rx_frontend
   output  logic[10:0]   frame_o,
   output  logic         parity_err_o,
   output  logic         frame_err_o,
-  output  logic         output_valid_o,
-  input logic test
+  output  logic         output_valid_o
 );
 
 rx_frontend dut (

From 568ba49e44722f8ef051c5832025f1cf347a5bd7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Cl=C3=A9ment=20Chaine?= <clement.chaine25@gmail.com>
Date: Sat, 6 Dec 2025 19:21:17 +0100
Subject: [PATCH 10/15] Use verilator-cmake v1.1.0

---
 CMakeLists.txt       | 2 +-
 tests/CMakeLists.txt | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 40ea049..5483f61 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -48,7 +48,7 @@ add_dependency(
 
 add_dependency(
   GIT ecap5/verilator-cmake
-  TAG tags/v1.0.1)
+  TAG release/v1.1.0)
 
 add_dependency(
   GIT ecap5/ecap5-treq
diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt
index 370b5f0..06137aa 100644
--- a/tests/CMakeLists.txt
+++ b/tests/CMakeLists.txt
@@ -29,7 +29,7 @@ set(TESTDATA_DIR ${CMAKE_CURRENT_BINARY_DIR}/)
 # Lint
 add_lint_target(
   TARGET lint
-  LIB    ecap5_dwbmmsc
+  LIB    ecap5_dwbuart
 )
 
 # Add testbenches

From 676119f392199934f2f44b87e51ce833762813ff Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Cl=C3=A9ment=20Chaine?= <clement.chaine25@gmail.com>
Date: Sat, 6 Dec 2025 19:30:48 +0100
Subject: [PATCH 11/15] Fix linting issues

---
 src/ecap5_dwbuart.sv | 26 +++++++++++++-------------
 src/rx_frontend.sv   |  6 +++---
 src/tx_frontend.sv   |  4 ++--
 3 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/src/ecap5_dwbuart.sv b/src/ecap5_dwbuart.sv
index 0fdf5e6..404fcbd 100644
--- a/src/ecap5_dwbuart.sv
+++ b/src/ecap5_dwbuart.sv
@@ -21,21 +21,21 @@
  */
 
 module ecap5_dwbuart #(
-  localparam UART_SR   = 0,
-  localparam UART_CR   = 1,
-  localparam UART_RXDR = 2,
-  localparam UART_TXDR = 3,
+  localparam logic[2:0] UART_SR   = 0,
+  localparam logic[2:0] UART_CR   = 1,
+  localparam logic[2:0] UART_RXDR = 2,
+  localparam logic[2:0] UART_TXDR = 3,
 
   // The minimum frame size is :
   //   - 7 data bits
   //   - 1 stop bit
-  localparam MIN_FRAME_SIZE = 8,
+  localparam logic[3:0] MIN_FRAME_SIZE = 8,
   
   // The maximum frame size is :
   //   - 8 data bits
   //   - 1 parity bit
   //   - 2 stop bit
-  localparam MAX_FRAME_SIZE = 11
+  localparam logic[3:0] MAX_FRAME_SIZE = 11
 )(
   input   logic         clk_i,
   input   logic         rst_i,
@@ -169,7 +169,7 @@ always_comb begin : register_access
 
   // Set the data output for read requests
   mem_read_data_d = 0;
-  case(mem_addr[7:2])
+  case(mem_addr[4:2])
     UART_SR:   mem_read_data_d = {27'b0, sr_pe_q, sr_fe_q, sr_rxoe_q, sr_txe_q, sr_rxne_q};
     UART_CR:   mem_read_data_d = {cr_acc_incr_q, 12'b0, cr_ds_q, cr_s_q, cr_p_q};
     UART_RXDR: mem_read_data_d = {24'b0, rxdr_rxd_q};
@@ -178,7 +178,7 @@ always_comb begin : register_access
 
   // Set the register data for write requests
   if(mem_write) begin
-    case(mem_addr[7:2])
+    case(mem_addr[4:2])
       UART_CR: begin
         cr_acc_incr_d = mem_write_data[31:16];
         cr_ds_d = mem_write_data[3];
@@ -193,7 +193,7 @@ always_comb begin : register_access
   end
 
   // Priority to the memory request
-  if(mem_write && (mem_addr[7:2] == UART_TXDR)) begin
+  if(mem_write && (mem_addr[4:2] == UART_TXDR)) begin
     sr_txe_d = 0;
   end else if (tx_done) begin
     sr_txe_d = 1;
@@ -214,12 +214,12 @@ always_comb begin : register_access
     end
   // When the memory request occurs but no data was received
   // we clear the previously received data
-  end else if(mem_read && mem_addr[7:2] == UART_RXDR) begin
+  end else if(mem_read && mem_addr[4:2] == UART_RXDR) begin
     rxdr_rxd_d = '0;
     sr_rxne_d = 0;
   // When the memory request occurs but no data was received
   // we clear the errors
-  end else if(mem_read && mem_addr[7:2] == UART_SR) begin
+  end else if(mem_read && mem_addr[4:2] == UART_SR) begin
     sr_pe_d = 0;
     sr_fe_d = 0;
     sr_rxoe_d = 0;
@@ -228,10 +228,10 @@ end
 
 always_comb begin : frontend_interface
   // Reset the frontends after either a reset or a write to UART_CR
-  frontend_rst = rst_i || (mem_write && mem_addr[7:2] == UART_CR);
+  frontend_rst = rst_i || (mem_write && mem_addr[4:2] == UART_CR);
 
   // Transmit after a write to UART_TXDR
-  tx_transmit_d = mem_write && (mem_addr[7:2] == UART_TXDR);
+  tx_transmit_d = mem_write && (mem_addr[4:2] == UART_TXDR);
 end
 
 always_ff @(posedge clk_i) begin
diff --git a/src/rx_frontend.sv b/src/rx_frontend.sv
index a0d0b19..b4e60df 100644
--- a/src/rx_frontend.sv
+++ b/src/rx_frontend.sv
@@ -21,8 +21,8 @@
  */
 
 module rx_frontend #(
-  parameter MIN_FRAME_SIZE = 8,
-  parameter MAX_FRAME_SIZE = 11
+  parameter logic[3:0] MIN_FRAME_SIZE = 8,
+  parameter logic[3:0] MAX_FRAME_SIZE = 11
 )(
   input   logic         clk_i,
   input   logic         rst_i,
@@ -54,7 +54,7 @@ state_t state_d, state_q;
 logic uart_rx_q, uart_rx_qq, uart_rx_qqq;
 
 logic[16:0] baud_acc_d, baud_acc_q;
-logic baud_acc_half_overflow, baud_acc_overflow;;
+logic baud_acc_half_overflow, baud_acc_overflow;
 
 logic[MAX_FRAME_SIZE:0]  frame_bit_cnt_d, frame_bit_cnt_q;
 
diff --git a/src/tx_frontend.sv b/src/tx_frontend.sv
index 74794ef..0692614 100644
--- a/src/tx_frontend.sv
+++ b/src/tx_frontend.sv
@@ -21,8 +21,8 @@
  */
 
 module tx_frontend #(
-  parameter MIN_FRAME_SIZE = 8,
-  parameter MAX_FRAME_SIZE = 11
+  parameter logic[3:0] MIN_FRAME_SIZE = 8,
+  parameter logic[3:0] MAX_FRAME_SIZE = 11
 )(
   input   logic         clk_i,
   input   logic         rst_i,

From 6d865002d0aae0fcd4606af9e6e0a0e90aacb779 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Cl=C3=A9ment=20Chaine?= <clement.chaine25@gmail.com>
Date: Sat, 27 Dec 2025 17:13:07 +0100
Subject: [PATCH 12/15] Fix unregistered transmit output

---
 config/traceability-matrix.csv                |  60 +-
 src/tx_frontend.sv                            |   8 +-
 .../ecap5_dwbuart/tb_ecap5_dwbuart.cpp        |  99 +--
 tests/benches/tx_frontend/tb_tx_frontend.cpp  | 609 +++++++-----------
 4 files changed, 322 insertions(+), 454 deletions(-)

diff --git a/config/traceability-matrix.csv b/config/traceability-matrix.csv
index 6a41b66..5d505ba 100644
--- a/config/traceability-matrix.csv
+++ b/config/traceability-matrix.csv
@@ -87,42 +87,30 @@ tb_rx_frontend.framing.03
 tb_tx_frontend.idle.01
 tb_tx_frontend.idle.02
 tb_tx_frontend.idle.03
-tb_tx_frontend.7N1.01
-tb_tx_frontend.7N1.02;F_UART_01;F_UART_02;F_TRANSMIT_01
-tb_tx_frontend.7N1.03;F_UART_02;F_UART_03;F_TRANSMIT_01
-tb_tx_frontend.7N2.01
-tb_tx_frontend.7N2.02;F_UART_01;F_UART_02;F_TRANSMIT_01
-tb_tx_frontend.7N2.03;F_UART_02;F_UART_03;F_TRANSMIT_01
-tb_tx_frontend.7E1.01
-tb_tx_frontend.7E1.02;F_UART_01;F_UART_02;F_TRANSMIT_01
-tb_tx_frontend.7E1.03;F_UART_02;F_UART_03;F_TRANSMIT_01
-tb_tx_frontend.7E2.01
-tb_tx_frontend.7E2.02;F_UART_01;F_UART_02;F_TRANSMIT_01
-tb_tx_frontend.7E2.03;F_UART_02;F_UART_03;F_TRANSMIT_01
-tb_tx_frontend.7O1.01
-tb_tx_frontend.7O1.02;F_UART_01;F_UART_02;F_TRANSMIT_01
-tb_tx_frontend.7O1.03;F_UART_02;F_UART_03;F_TRANSMIT_01
-tb_tx_frontend.7O2.01
-tb_tx_frontend.7O2.02;F_UART_01;F_UART_02;F_TRANSMIT_01
-tb_tx_frontend.7O2.03;F_UART_02;F_UART_03;F_TRANSMIT_01
-tb_tx_frontend.8N1.01
-tb_tx_frontend.8N1.02;F_UART_01;F_UART_02;F_TRANSMIT_01
-tb_tx_frontend.8N1.03;F_UART_02;F_UART_03;F_TRANSMIT_01
-tb_tx_frontend.8N2.01
-tb_tx_frontend.8N2.02;F_UART_01;F_UART_02;F_TRANSMIT_01
-tb_tx_frontend.8N2.03;F_UART_02;F_UART_03;F_TRANSMIT_01
-tb_tx_frontend.8E1.01
-tb_tx_frontend.8E1.02;F_UART_01;F_UART_02;F_TRANSMIT_01
-tb_tx_frontend.8E1.03;F_UART_02;F_UART_03;F_TRANSMIT_01
-tb_tx_frontend.8E2.01
-tb_tx_frontend.8E2.02;F_UART_01;F_UART_02;F_TRANSMIT_01
-tb_tx_frontend.8E2.03;F_UART_02;F_UART_03;F_TRANSMIT_01
-tb_tx_frontend.8O1.01
-tb_tx_frontend.8O1.02;F_UART_01;F_UART_02;F_TRANSMIT_01
-tb_tx_frontend.8O1.03;F_UART_02;F_UART_03;F_TRANSMIT_01
-tb_tx_frontend.8O2.01
-tb_tx_frontend.8O2.02;F_UART_01;F_UART_02;F_TRANSMIT_01
-tb_tx_frontend.8O2.03;F_UART_02;F_UART_03;F_TRANSMIT_01
+tb_tx_frontend.7N1.01;F_UART_01;F_UART_02;F_TRANSMIT_01
+tb_tx_frontend.7N1.02;F_UART_02;F_UART_03;F_TRANSMIT_01
+tb_tx_frontend.7N2.01;F_UART_01;F_UART_02;F_TRANSMIT_01
+tb_tx_frontend.7N2.02;F_UART_02;F_UART_03;F_TRANSMIT_01
+tb_tx_frontend.7E1.01;F_UART_01;F_UART_02;F_TRANSMIT_01
+tb_tx_frontend.7E1.02;F_UART_02;F_UART_03;F_TRANSMIT_01
+tb_tx_frontend.7E2.01;F_UART_01;F_UART_02;F_TRANSMIT_01
+tb_tx_frontend.7E2.02;F_UART_02;F_UART_03;F_TRANSMIT_01
+tb_tx_frontend.7O1.01;F_UART_01;F_UART_02;F_TRANSMIT_01
+tb_tx_frontend.7O1.02;F_UART_02;F_UART_03;F_TRANSMIT_01
+tb_tx_frontend.7O2.01;F_UART_01;F_UART_02;F_TRANSMIT_01
+tb_tx_frontend.7O2.02;F_UART_02;F_UART_03;F_TRANSMIT_01
+tb_tx_frontend.8N1.01;F_UART_01;F_UART_02;F_TRANSMIT_01
+tb_tx_frontend.8N1.02;F_UART_02;F_UART_03;F_TRANSMIT_01
+tb_tx_frontend.8N2.01;F_UART_01;F_UART_02;F_TRANSMIT_01
+tb_tx_frontend.8N2.02;F_UART_02;F_UART_03;F_TRANSMIT_01
+tb_tx_frontend.8E1.01;F_UART_01;F_UART_02;F_TRANSMIT_01
+tb_tx_frontend.8E1.02;F_UART_02;F_UART_03;F_TRANSMIT_01
+tb_tx_frontend.8E2.01;F_UART_01;F_UART_02;F_TRANSMIT_01
+tb_tx_frontend.8E2.02;F_UART_02;F_UART_03;F_TRANSMIT_01
+tb_tx_frontend.8O1.01;F_UART_01;F_UART_02;F_TRANSMIT_01
+tb_tx_frontend.8O1.02;F_UART_02;F_UART_03;F_TRANSMIT_01
+tb_tx_frontend.8O2.01;F_UART_01;F_UART_02;F_TRANSMIT_01
+tb_tx_frontend.8O2.02;F_UART_02;F_UART_03;F_TRANSMIT_01
 tb_tx_frontend.baudrate.01
 tb_tx_frontend.baudrate.02;F_UART_01;F_UART_02;F_TRANSMIT_01
 tb_tx_frontend.baudrate.03;F_UART_02;F_UART_03;F_TRANSMIT_01
diff --git a/src/tx_frontend.sv b/src/tx_frontend.sv
index 0692614..1fac333 100644
--- a/src/tx_frontend.sv
+++ b/src/tx_frontend.sv
@@ -69,7 +69,7 @@ logic parity_d, parity_q;
 /*            Output signals             */
 /*****************************************/
 
-logic uart_tx_d;
+logic uart_tx_d, uart_tx_q;
 
 logic done_d, done_q;
 
@@ -212,6 +212,8 @@ always_ff @(posedge clk_i) begin
     parity_q <= 0;
 
     done_q <= 0;
+
+    uart_tx_q <= 1;
   end else begin
     state_q <= state_d;
 
@@ -229,6 +231,8 @@ always_ff @(posedge clk_i) begin
 
     // Asserted to indicate the end of a transmission
     done_q <= done_d;
+
+    uart_tx_q <= uart_tx_d;
   end
 end
 
@@ -236,7 +240,7 @@ end
 /*         Assign output signals         */
 /*****************************************/
 
-assign uart_tx_o = rst_i ? 1 : uart_tx_d;
+assign uart_tx_o = uart_tx_q;
 assign done_o = done_q;
 
 endmodule // tx_frontend
diff --git a/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.cpp b/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.cpp
index fd1b6a0..2eaa47d 100644
--- a/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.cpp
+++ b/tests/benches/ecap5_dwbuart/tb_ecap5_dwbuart.cpp
@@ -575,11 +575,6 @@ void tb_ecap5_dwbuart_read_rxdr(TB_Ecap5_dwbuart * tb) {
   
   tb->tick();
 
-  //`````````````````````````````````
-  //      Checks 
-  
-  tb->check(COND_rx, (core->tb_ecap5_dwbuart->dut->rx_valid == 1));
-
   //=================================
   //      Tick (51)
   
@@ -588,9 +583,7 @@ void tb_ecap5_dwbuart_read_rxdr(TB_Ecap5_dwbuart * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_rx, (core->tb_ecap5_dwbuart->dut->rx_valid == 0));
-  tb->check(COND_registers, (tb->uart_rxdr() == 0xA5) &&
-                            (tb->uart_sr() & 0x1));
+  tb->check(COND_rx, (core->tb_ecap5_dwbuart->dut->rx_valid == 1));
 
   //=================================
   //      Tick (52)
@@ -600,6 +593,7 @@ void tb_ecap5_dwbuart_read_rxdr(TB_Ecap5_dwbuart * tb) {
   //`````````````````````````````````
   //      Checks 
   
+  tb->check(COND_rx, (core->tb_ecap5_dwbuart->dut->rx_valid == 0));
   tb->check(COND_registers, (tb->uart_rxdr() == 0xA5) &&
                             (tb->uart_sr() & 0x1));
 
@@ -676,20 +670,24 @@ void tb_ecap5_dwbuart_rxoe(TB_Ecap5_dwbuart * tb) {
   
   tb->tick();
 
+  //=================================
+  //      Tick (98)
+  
+  tb->tick();
+
   //`````````````````````````````````
   //      Checks 
   
   tb->check(COND_rx, (core->tb_ecap5_dwbuart->dut->rx_valid == 1));
 
   //=================================
-  //      Tick (98)
+  //      Tick (99)
   
   tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_rx, (core->tb_ecap5_dwbuart->dut->rx_valid == 0));
   tb->check(COND_registers, ((tb->uart_sr() >> 2) & 0x1) &&
                              (tb->uart_rxdr() == 0xFA));
 
@@ -699,13 +697,14 @@ void tb_ecap5_dwbuart_rxoe(TB_Ecap5_dwbuart * tb) {
   tb->read(0x8);
 
   //=================================
-  //      Tick (99)
+  //      Tick (100)
   
   tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
+  tb->check(COND_rx, (core->tb_ecap5_dwbuart->dut->rx_valid == 0));
   tb->check(COND_mem, (core->tb_ecap5_dwbuart->dut->mem_read_data_q == 0xFA));
   tb->check(COND_registers, ((tb->uart_sr() >> 2) & 0x1) &&
                              (tb->uart_rxdr() == 0x0));
@@ -717,7 +716,7 @@ void tb_ecap5_dwbuart_rxoe(TB_Ecap5_dwbuart * tb) {
   core->wb_cyc_i = 1;
 
   //=================================
-  //      Tick (100)
+  //      Tick (101)
   
   tb->tick();
 
@@ -727,7 +726,7 @@ void tb_ecap5_dwbuart_rxoe(TB_Ecap5_dwbuart * tb) {
   tb->_nop();
 
   //=================================
-  //      Tick (101)
+  //      Tick (102)
   
   tb->tick();
 
@@ -739,7 +738,7 @@ void tb_ecap5_dwbuart_rxoe(TB_Ecap5_dwbuart * tb) {
   uint32_t sr = tb->uart_sr();
 
   //=================================
-  //      Tick (102)
+  //      Tick (103)
   
   tb->tick();
 
@@ -756,7 +755,7 @@ void tb_ecap5_dwbuart_rxoe(TB_Ecap5_dwbuart * tb) {
   core->wb_cyc_i = 1;
 
   //=================================
-  //      Tick (103)
+  //      Tick (104)
   
   tb->tick();
 
@@ -766,7 +765,7 @@ void tb_ecap5_dwbuart_rxoe(TB_Ecap5_dwbuart * tb) {
   tb->_nop();
 
   //=================================
-  //      Tick (104)
+  //      Tick (105)
   
   tb->tick();
 
@@ -805,6 +804,11 @@ void tb_ecap5_dwbuart_fe(TB_Ecap5_dwbuart * tb) {
   
   tb->tick();
 
+  //=================================
+  //      Tick (49)
+  
+  tb->tick();
+
   //`````````````````````````````````
   //      Set inputs
 
@@ -813,7 +817,7 @@ void tb_ecap5_dwbuart_fe(TB_Ecap5_dwbuart * tb) {
   uint32_t sr = tb->uart_sr();
 
   //=================================
-  //      Tick (49)
+  //      Tick (50)
   
   tb->tick();
 
@@ -830,7 +834,7 @@ void tb_ecap5_dwbuart_fe(TB_Ecap5_dwbuart * tb) {
   core->wb_cyc_i = 1;
 
   //=================================
-  //      Tick (50)
+  //      Tick (51)
   
   tb->tick();
 
@@ -840,7 +844,7 @@ void tb_ecap5_dwbuart_fe(TB_Ecap5_dwbuart * tb) {
   tb->_nop();
 
   //=================================
-  //      Tick (51)
+  //      Tick (52)
   
   tb->tick();
 
@@ -958,6 +962,11 @@ void tb_ecap5_dwbuart_error_retention(TB_Ecap5_dwbuart * tb) {
   // Check that every errors is still present
   tb->check(COND_registers, ((tb->uart_sr() >> 2) & 0x7) == 0x7);
 
+  //=================================
+  //      Tick (251)
+  
+  tb->tick();
+
   //`````````````````````````````````
   //      Set inputs
   
@@ -965,7 +974,7 @@ void tb_ecap5_dwbuart_error_retention(TB_Ecap5_dwbuart * tb) {
   uint32_t sr = tb->uart_sr();
 
   //=================================
-  //      Tick (251)
+  //      Tick (252)
   
   tb->tick();
 
@@ -982,7 +991,7 @@ void tb_ecap5_dwbuart_error_retention(TB_Ecap5_dwbuart * tb) {
   core->wb_cyc_i = 1;
 
   //=================================
-  //      Tick (252)
+  //      Tick (253)
   
   tb->tick();
 
@@ -992,7 +1001,7 @@ void tb_ecap5_dwbuart_error_retention(TB_Ecap5_dwbuart * tb) {
   tb->_nop();
 
   //=================================
-  //      Tick (253)
+  //      Tick (254)
   
   tb->tick();
 
@@ -1029,7 +1038,12 @@ void tb_ecap5_dwbuart_race_sr(TB_Ecap5_dwbuart * tb) {
   tb->read(0x0);
 
   //=================================
-  //      Tick (50)
+  //      Tick (51)
+  
+  tb->tick();
+
+  //=================================
+  //      Tick (52)
   
   tb->tick();
 
@@ -1046,7 +1060,7 @@ void tb_ecap5_dwbuart_race_sr(TB_Ecap5_dwbuart * tb) {
   core->wb_cyc_i = 1;
 
   //=================================
-  //      Tick (50)
+  //      Tick (53)
   
   tb->tick();
 
@@ -1056,7 +1070,7 @@ void tb_ecap5_dwbuart_race_sr(TB_Ecap5_dwbuart * tb) {
   tb->_nop();
 
   //=================================
-  //      Tick (51)
+  //      Tick (54)
   
   tb->tick();
   
@@ -1066,7 +1080,7 @@ void tb_ecap5_dwbuart_race_sr(TB_Ecap5_dwbuart * tb) {
   tb->read(0x0);
 
   //=================================
-  //      Tick (49)
+  //      Tick (55)
   
   tb->tick();
 
@@ -1083,7 +1097,7 @@ void tb_ecap5_dwbuart_race_sr(TB_Ecap5_dwbuart * tb) {
   core->wb_cyc_i = 1;
 
   //=================================
-  //      Tick (50)
+  //      Tick (56)
   
   tb->tick();
 
@@ -1093,7 +1107,7 @@ void tb_ecap5_dwbuart_race_sr(TB_Ecap5_dwbuart * tb) {
   tb->_nop();
 
   //=================================
-  //      Tick (51)
+  //      Tick (57)
   
   tb->tick();
 
@@ -1124,13 +1138,18 @@ void tb_ecap5_dwbuart_race_txdr(TB_Ecap5_dwbuart * tb) {
 
   tb->generate_read();
 
+  //=================================
+  //      Tick (50)
+  
+  tb->tick();
+
   //`````````````````````````````````
   //      Set inputs
   
   tb->write(0xC, 0xA5FA5FA5);
 
   //=================================
-  //      Tick (4)
+  //      Tick (51)
   
   tb->tick();
 
@@ -1148,7 +1167,7 @@ void tb_ecap5_dwbuart_race_txdr(TB_Ecap5_dwbuart * tb) {
   core->wb_cyc_i = 1;
 
   //=================================
-  //      Tick (5)
+  //      Tick (52)
   
   tb->tick();
 
@@ -1187,6 +1206,14 @@ void tb_ecap5_dwbuart_race_rxdr(TB_Ecap5_dwbuart * tb) {
 
   tb->generate_read();
 
+  //=================================
+  //      Tick (50)
+  
+  tb->tick();
+
+  //=================================
+  //      Tick (51)
+  
   tb->tick();
 
   //`````````````````````````````````
@@ -1195,7 +1222,7 @@ void tb_ecap5_dwbuart_race_rxdr(TB_Ecap5_dwbuart * tb) {
   tb->read(0x8);
 
   //=================================
-  //      Tick (53)
+  //      Tick (52)
   
   tb->tick();
 
@@ -1212,7 +1239,7 @@ void tb_ecap5_dwbuart_race_rxdr(TB_Ecap5_dwbuart * tb) {
   core->wb_cyc_i = 1;
 
   //=================================
-  //      Tick (52)
+  //      Tick (53)
   
   tb->tick();
 
@@ -1222,7 +1249,7 @@ void tb_ecap5_dwbuart_race_rxdr(TB_Ecap5_dwbuart * tb) {
   tb->_nop();
 
   //=================================
-  //      Tick (53)
+  //      Tick (54)
   
   tb->tick();
 
@@ -1232,7 +1259,7 @@ void tb_ecap5_dwbuart_race_rxdr(TB_Ecap5_dwbuart * tb) {
   tb->read(0x8);
 
   //=================================
-  //      Tick (53)
+  //      Tick (55)
   
   tb->tick();
 
@@ -1250,7 +1277,7 @@ void tb_ecap5_dwbuart_race_rxdr(TB_Ecap5_dwbuart * tb) {
   core->wb_cyc_i = 1;
 
   //=================================
-  //      Tick (52)
+  //      Tick (56)
   
   tb->tick();
 
@@ -1260,7 +1287,7 @@ void tb_ecap5_dwbuart_race_rxdr(TB_Ecap5_dwbuart * tb) {
   tb->_nop();
 
   //=================================
-  //      Tick (53)
+  //      Tick (57)
   
   tb->tick();
 
diff --git a/tests/benches/tx_frontend/tb_tx_frontend.cpp b/tests/benches/tx_frontend/tb_tx_frontend.cpp
index 4f0ddff..2ceedb0 100644
--- a/tests/benches/tx_frontend/tb_tx_frontend.cpp
+++ b/tests/benches/tx_frontend/tb_tx_frontend.cpp
@@ -33,7 +33,6 @@
 #include "testbench.h"
 
 enum CondId {
-  COND_state,
   COND_output,
   COND_done,
   COND_baudrate,
@@ -141,7 +140,6 @@ void tb_tx_frontend_idle(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
   tb->check(COND_output, (core->uart_tx_o == 1));
   tb->check(COND_done,   (core->done_o == 0));
   
@@ -153,7 +151,6 @@ void tb_tx_frontend_idle(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
   tb->check(COND_output, (core->uart_tx_o == 1));
   tb->check(COND_done,   (core->done_o == 0));
 
@@ -165,7 +162,6 @@ void tb_tx_frontend_idle(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
   tb->check(COND_output, (core->uart_tx_o == 1));
   tb->check(COND_done,   (core->done_o == 0));
 
@@ -177,7 +173,6 @@ void tb_tx_frontend_idle(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
   tb->check(COND_output, (core->uart_tx_o == 1));
   tb->check(COND_done,   (core->done_o == 0));
 
@@ -185,14 +180,10 @@ void tb_tx_frontend_idle(TB_Tx_frontend * tb) {
   //      Formal Checks 
   
   CHECK("tb_tx_frontend.idle.01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
-
-  CHECK("tb_tx_frontend.idle.02",
       tb->conditions[COND_output],
       "Failed to implement the output signal", tb->err_cycles[COND_output]);
 
-  CHECK("tb_tx_frontend.idle.03",
+  CHECK("tb_tx_frontend.idle.02",
       tb->conditions[COND_done],
       "Failed to implement the done signal", tb->err_cycles[COND_done]);
 }
@@ -223,10 +214,14 @@ void tb_tx_frontend_7N1(TB_Tx_frontend * tb) {
   
   tb->tick();
 
+  //=================================
+  //      Tick (2)
+  
+  tb->tick();
+
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
   tb->check(COND_output, (core->uart_tx_o == 0));
   tb->check(COND_done,   (core->done_o == 0));
 
@@ -236,7 +231,7 @@ void tb_tx_frontend_7N1(TB_Tx_frontend * tb) {
   core->transmit_i = 0;
 
   //=================================
-  //      Tick (2-10)
+  //      Tick (3-11)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -244,13 +239,12 @@ void tb_tx_frontend_7N1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (11-20)
+  //      Tick (12-21)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -258,13 +252,12 @@ void tb_tx_frontend_7N1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (21-29)
+  //      Tick (22-30)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -272,13 +265,12 @@ void tb_tx_frontend_7N1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (30-39)
+  //      Tick (31-40)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -286,13 +278,12 @@ void tb_tx_frontend_7N1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (40-49)
+  //      Tick (41-50)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -300,13 +291,12 @@ void tb_tx_frontend_7N1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (50-58)
+  //      Tick (51-59)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -314,13 +304,12 @@ void tb_tx_frontend_7N1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (59-68)
+  //      Tick (60-69)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -328,13 +317,12 @@ void tb_tx_frontend_7N1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (69-77)
+  //      Tick (70-78)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -342,21 +330,19 @@ void tb_tx_frontend_7N1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (78-87)
+  //      Tick (79-87)
   
-  for(size_t i = 0; i < 10; i++) {
+  for(size_t i = 0; i < 9; i++) {
     tb->tick();
 
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
@@ -369,7 +355,7 @@ void tb_tx_frontend_7N1(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
+  tb->check(COND_output, (core->uart_tx_o == 1));
   tb->check(COND_done,   (core->done_o == 1));
 
   //=================================
@@ -380,21 +366,16 @@ void tb_tx_frontend_7N1(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
   tb->check(COND_done,   (core->done_o == 0));
 
   //`````````````````````````````````
   //      Formal Checks 
   
   CHECK("tb_tx_frontend.7N1.01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
-
-  CHECK("tb_tx_frontend.7N1.02",
       tb->conditions[COND_output],
       "Failed to implement the output signal", tb->err_cycles[COND_output]);
 
-  CHECK("tb_tx_frontend.7N1.03",
+  CHECK("tb_tx_frontend.7N1.02",
       tb->conditions[COND_done],
       "Failed to implement the done signal", tb->err_cycles[COND_done]);
 }
@@ -425,10 +406,14 @@ void tb_tx_frontend_7N2(TB_Tx_frontend * tb) {
   
   tb->tick();
 
+  //=================================
+  //      Tick (2)
+  
+  tb->tick();
+
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
   tb->check(COND_output, (core->uart_tx_o == 0));
   tb->check(COND_done,   (core->done_o == 0));
 
@@ -438,7 +423,7 @@ void tb_tx_frontend_7N2(TB_Tx_frontend * tb) {
   core->transmit_i = 0;
 
   //=================================
-  //      Tick (2-10)
+  //      Tick (3-11)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -446,13 +431,12 @@ void tb_tx_frontend_7N2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (11-20)
+  //      Tick (12-21)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -460,13 +444,12 @@ void tb_tx_frontend_7N2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (21-29)
+  //      Tick (22-30)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -474,13 +457,12 @@ void tb_tx_frontend_7N2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (30-39)
+  //      Tick (31-40)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -488,13 +470,12 @@ void tb_tx_frontend_7N2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (40-49)
+  //      Tick (41-50)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -502,13 +483,12 @@ void tb_tx_frontend_7N2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (50-58)
+  //      Tick (51-59)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -516,13 +496,12 @@ void tb_tx_frontend_7N2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (59-68)
+  //      Tick (60-69)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -530,13 +509,12 @@ void tb_tx_frontend_7N2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (69-77)
+  //      Tick (70-78)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -544,13 +522,12 @@ void tb_tx_frontend_7N2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (78-87)
+  //      Tick (79-88)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -558,21 +535,19 @@ void tb_tx_frontend_7N2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (88-96)
+  //      Tick (89-96)
   
-  for(size_t i = 0; i < 9; i++) {
+  for(size_t i = 0; i < 8; i++) {
     tb->tick();
 
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
@@ -585,7 +560,7 @@ void tb_tx_frontend_7N2(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
+  tb->check(COND_output, (core->uart_tx_o == 1));
   tb->check(COND_done,   (core->done_o == 1));
 
   //=================================
@@ -596,21 +571,16 @@ void tb_tx_frontend_7N2(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
   tb->check(COND_done,   (core->done_o == 0));
 
   //`````````````````````````````````
   //      Formal Checks 
-  
-  CHECK("tb_tx_frontend.7N2.01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
 
-  CHECK("tb_tx_frontend.7N2.02",
+  CHECK("tb_tx_frontend.7N2.01",
       tb->conditions[COND_output],
       "Failed to implement the output signal", tb->err_cycles[COND_output]);
 
-  CHECK("tb_tx_frontend.7N2.03",
+  CHECK("tb_tx_frontend.7N2.02",
       tb->conditions[COND_done],
       "Failed to implement the done signal", tb->err_cycles[COND_done]);
 }
@@ -641,10 +611,14 @@ void tb_tx_frontend_7E1(TB_Tx_frontend * tb) {
   
   tb->tick();
 
+  //=================================
+  //      Tick (2)
+  
+  tb->tick();
+
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
   tb->check(COND_output, (core->uart_tx_o == 0));
   tb->check(COND_done,   (core->done_o == 0));
 
@@ -654,7 +628,7 @@ void tb_tx_frontend_7E1(TB_Tx_frontend * tb) {
   core->transmit_i = 0;
 
   //=================================
-  //      Tick (2-10)
+  //      Tick (3-11)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -662,13 +636,12 @@ void tb_tx_frontend_7E1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (11-20)
+  //      Tick (12-21)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -676,13 +649,12 @@ void tb_tx_frontend_7E1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (21-29)
+  //      Tick (22-30)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -690,13 +662,12 @@ void tb_tx_frontend_7E1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (30-39)
+  //      Tick (31-40)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -704,13 +675,12 @@ void tb_tx_frontend_7E1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (40-49)
+  //      Tick (41-50)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -718,13 +688,12 @@ void tb_tx_frontend_7E1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (50-58)
+  //      Tick (51-59)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -732,13 +701,12 @@ void tb_tx_frontend_7E1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (59-68)
+  //      Tick (60-69)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -746,13 +714,12 @@ void tb_tx_frontend_7E1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (69-77)
+  //      Tick (70-78)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -760,13 +727,12 @@ void tb_tx_frontend_7E1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (78-87)
+  //      Tick (79-88)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -774,21 +740,19 @@ void tb_tx_frontend_7E1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_PARITY));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (88-96)
+  //      Tick (89-96)
   
-  for(size_t i = 0; i < 9; i++) {
+  for(size_t i = 0; i < 8; i++) {
     tb->tick();
 
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
@@ -801,33 +765,27 @@ void tb_tx_frontend_7E1(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
+  tb->check(COND_output, (core->uart_tx_o == 1));
   tb->check(COND_done,   (core->done_o == 1));
 
   //=================================
-  //      Tick (98)
+  //      Tick (99)
   
   tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
   tb->check(COND_done,   (core->done_o == 0));
 
-
   //`````````````````````````````````
   //      Formal Checks 
   
   CHECK("tb_tx_frontend.7E1.01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
-
-  CHECK("tb_tx_frontend.7E1.02",
       tb->conditions[COND_output],
       "Failed to implement the output signal", tb->err_cycles[COND_output]);
 
-  CHECK("tb_tx_frontend.7E1.03",
+  CHECK("tb_tx_frontend.7E1.02",
       tb->conditions[COND_done],
       "Failed to implement the done signal", tb->err_cycles[COND_done]);
   
@@ -859,10 +817,14 @@ void tb_tx_frontend_7E2(TB_Tx_frontend * tb) {
   
   tb->tick();
 
+  //=================================
+  //      Tick (2)
+  
+  tb->tick();
+
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
   tb->check(COND_output, (core->uart_tx_o == 0));
   tb->check(COND_done,   (core->done_o == 0));
 
@@ -872,7 +834,7 @@ void tb_tx_frontend_7E2(TB_Tx_frontend * tb) {
   core->transmit_i = 0;
 
   //=================================
-  //      Tick (2-10)
+  //      Tick (3-11)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -880,13 +842,12 @@ void tb_tx_frontend_7E2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (11-20)
+  //      Tick (12-21)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -894,13 +855,12 @@ void tb_tx_frontend_7E2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (21-29)
+  //      Tick (22-30)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -908,13 +868,12 @@ void tb_tx_frontend_7E2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (30-39)
+  //      Tick (31-40)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -922,13 +881,12 @@ void tb_tx_frontend_7E2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (40-49)
+  //      Tick (41-50)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -936,13 +894,12 @@ void tb_tx_frontend_7E2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (50-58)
+  //      Tick (51-59)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -950,13 +907,12 @@ void tb_tx_frontend_7E2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (59-68)
+  //      Tick (60-69)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -964,13 +920,12 @@ void tb_tx_frontend_7E2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (69-77)
+  //      Tick (70-78)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -978,13 +933,12 @@ void tb_tx_frontend_7E2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (78-87)
+  //      Tick (79-88)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -992,13 +946,12 @@ void tb_tx_frontend_7E2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_PARITY));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (88-96)
+  //      Tick (89-97)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -1006,21 +959,19 @@ void tb_tx_frontend_7E2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (97-106)
+  //      Tick (98-106)
   
-  for(size_t i = 0; i < 10; i++) {
+  for(size_t i = 0; i < 9; i++) {
     tb->tick();
 
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
@@ -1033,7 +984,7 @@ void tb_tx_frontend_7E2(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
+  tb->check(COND_output, (core->uart_tx_o == 1));
   tb->check(COND_done,   (core->done_o == 1));
 
   //=================================
@@ -1044,21 +995,16 @@ void tb_tx_frontend_7E2(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
   tb->check(COND_done,   (core->done_o == 0));
 
   //`````````````````````````````````
   //      Formal Checks 
   
   CHECK("tb_tx_frontend.7E2.01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
-
-  CHECK("tb_tx_frontend.7E2.02",
       tb->conditions[COND_output],
       "Failed to implement the output signal", tb->err_cycles[COND_output]);
 
-  CHECK("tb_tx_frontend.7E2.03",
+  CHECK("tb_tx_frontend.7E2.02",
       tb->conditions[COND_done],
       "Failed to implement the done signal", tb->err_cycles[COND_done]);
 }
@@ -1089,10 +1035,14 @@ void tb_tx_frontend_7O1(TB_Tx_frontend * tb) {
   
   tb->tick();
 
+  //=================================
+  //      Tick (2)
+  
+  tb->tick();
+
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
   tb->check(COND_output, (core->uart_tx_o == 0));
   tb->check(COND_done,   (core->done_o == 0));
 
@@ -1102,7 +1052,7 @@ void tb_tx_frontend_7O1(TB_Tx_frontend * tb) {
   core->transmit_i = 0;
 
   //=================================
-  //      Tick (2-10)
+  //      Tick (3-11)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -1110,13 +1060,12 @@ void tb_tx_frontend_7O1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (11-20)
+  //      Tick (12-21)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -1124,13 +1073,12 @@ void tb_tx_frontend_7O1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (21-29)
+  //      Tick (22-30)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -1138,13 +1086,12 @@ void tb_tx_frontend_7O1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (30-39)
+  //      Tick (31-40)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -1152,13 +1099,12 @@ void tb_tx_frontend_7O1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (40-49)
+  //      Tick (41-50)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -1166,13 +1112,12 @@ void tb_tx_frontend_7O1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (50-58)
+  //      Tick (51-59)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -1180,13 +1125,12 @@ void tb_tx_frontend_7O1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (59-68)
+  //      Tick (60-69)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -1194,13 +1138,12 @@ void tb_tx_frontend_7O1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (69-77)
+  //      Tick (70-78)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -1208,13 +1151,12 @@ void tb_tx_frontend_7O1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (78-87)
+  //      Tick (79-88)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -1222,21 +1164,19 @@ void tb_tx_frontend_7O1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_PARITY));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (88-96)
+  //      Tick (89-96)
   
-  for(size_t i = 0; i < 9; i++) {
+  for(size_t i = 0; i < 8; i++) {
     tb->tick();
 
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
@@ -1249,7 +1189,7 @@ void tb_tx_frontend_7O1(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
+  tb->check(COND_output, (core->uart_tx_o == 1));
   tb->check(COND_done,   (core->done_o == 1));
 
   //=================================
@@ -1260,21 +1200,16 @@ void tb_tx_frontend_7O1(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
   tb->check(COND_done,   (core->done_o == 0));
 
   //`````````````````````````````````
   //      Formal Checks 
   
   CHECK("tb_tx_frontend.7O1.01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
-
-  CHECK("tb_tx_frontend.7O1.02",
       tb->conditions[COND_output],
       "Failed to implement the output signal", tb->err_cycles[COND_output]);
 
-  CHECK("tb_tx_frontend.7O1.03",
+  CHECK("tb_tx_frontend.7O1.02",
       tb->conditions[COND_done],
       "Failed to implement the done signal", tb->err_cycles[COND_done]);
 }
@@ -1305,10 +1240,14 @@ void tb_tx_frontend_7O2(TB_Tx_frontend * tb) {
   
   tb->tick();
 
+  //=================================
+  //      Tick (2)
+  
+  tb->tick();
+
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
   tb->check(COND_output, (core->uart_tx_o == 0));
   tb->check(COND_done,   (core->done_o == 0));
 
@@ -1318,7 +1257,7 @@ void tb_tx_frontend_7O2(TB_Tx_frontend * tb) {
   core->transmit_i = 0;
 
   //=================================
-  //      Tick (2-10)
+  //      Tick (3-11)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -1326,13 +1265,12 @@ void tb_tx_frontend_7O2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (11-20)
+  //      Tick (12-21)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -1340,13 +1278,12 @@ void tb_tx_frontend_7O2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (21-29)
+  //      Tick (22-30)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -1354,13 +1291,12 @@ void tb_tx_frontend_7O2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (30-39)
+  //      Tick (31-40)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -1368,13 +1304,12 @@ void tb_tx_frontend_7O2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (40-49)
+  //      Tick (41-50)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -1382,13 +1317,12 @@ void tb_tx_frontend_7O2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (50-58)
+  //      Tick (51-59)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -1396,13 +1330,12 @@ void tb_tx_frontend_7O2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (59-68)
+  //      Tick (60-69)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -1410,13 +1343,12 @@ void tb_tx_frontend_7O2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (69-77)
+  //      Tick (70-78)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -1424,13 +1356,12 @@ void tb_tx_frontend_7O2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (78-87)
+  //      Tick (79-88)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -1438,13 +1369,12 @@ void tb_tx_frontend_7O2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_PARITY));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (88-96)
+  //      Tick (89-97)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -1452,21 +1382,19 @@ void tb_tx_frontend_7O2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (97-106)
+  //      Tick (98-106)
   
-  for(size_t i = 0; i < 10; i++) {
+  for(size_t i = 0; i < 9; i++) {
     tb->tick();
 
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
@@ -1479,7 +1407,7 @@ void tb_tx_frontend_7O2(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
+  tb->check(COND_output, (core->uart_tx_o == 1));
   tb->check(COND_done,   (core->done_o == 1));
 
   //=================================
@@ -1490,21 +1418,16 @@ void tb_tx_frontend_7O2(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
   tb->check(COND_done,   (core->done_o == 0));
 
   //`````````````````````````````````
   //      Formal Checks 
   
   CHECK("tb_tx_frontend.7O2.01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
-
-  CHECK("tb_tx_frontend.7O2.02",
       tb->conditions[COND_output],
       "Failed to implement the output signal", tb->err_cycles[COND_output]);
 
-  CHECK("tb_tx_frontend.7O2.03",
+  CHECK("tb_tx_frontend.7O2.02",
       tb->conditions[COND_done],
       "Failed to implement the done signal", tb->err_cycles[COND_done]);
 }
@@ -1535,10 +1458,14 @@ void tb_tx_frontend_8N1(TB_Tx_frontend * tb) {
   
   tb->tick();
 
+  //=================================
+  //      Tick (2)
+  
+  tb->tick();
+
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
   tb->check(COND_output, (core->uart_tx_o == 0));
   tb->check(COND_done,   (core->done_o == 0));
 
@@ -1548,7 +1475,7 @@ void tb_tx_frontend_8N1(TB_Tx_frontend * tb) {
   core->transmit_i = 0;
 
   //=================================
-  //      Tick (2-10)
+  //      Tick (3-11)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -1556,13 +1483,12 @@ void tb_tx_frontend_8N1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (11-20)
+  //      Tick (12-21)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -1570,13 +1496,12 @@ void tb_tx_frontend_8N1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (21-29)
+  //      Tick (22-30)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -1584,13 +1509,12 @@ void tb_tx_frontend_8N1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (30-39)
+  //      Tick (31-40)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -1598,13 +1522,12 @@ void tb_tx_frontend_8N1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (40-49)
+  //      Tick (41-50)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -1612,13 +1535,12 @@ void tb_tx_frontend_8N1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (50-58)
+  //      Tick (51-59)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -1626,13 +1548,12 @@ void tb_tx_frontend_8N1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (59-68)
+  //      Tick (60-69)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -1640,13 +1561,12 @@ void tb_tx_frontend_8N1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (69-77)
+  //      Tick (70-78)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -1654,13 +1574,12 @@ void tb_tx_frontend_8N1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (78-87)
+  //      Tick (79-88)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -1668,21 +1587,19 @@ void tb_tx_frontend_8N1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (88-96)
+  //      Tick (89-96)
   
-  for(size_t i = 0; i < 9; i++) {
+  for(size_t i = 0; i < 8; i++) {
     tb->tick();
 
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
@@ -1695,7 +1612,7 @@ void tb_tx_frontend_8N1(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
+  tb->check(COND_output, (core->uart_tx_o == 1));
   tb->check(COND_done,   (core->done_o == 1));
 
   //=================================
@@ -1706,21 +1623,16 @@ void tb_tx_frontend_8N1(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
   tb->check(COND_done,   (core->done_o == 0));
 
   //`````````````````````````````````
   //      Formal Checks 
   
   CHECK("tb_tx_frontend.8N1.01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
-
-  CHECK("tb_tx_frontend.8N1.02",
       tb->conditions[COND_output],
       "Failed to implement the output signal", tb->err_cycles[COND_output]);
 
-  CHECK("tb_tx_frontend.8N1.03",
+  CHECK("tb_tx_frontend.8N1.02",
       tb->conditions[COND_done],
       "Failed to implement the done signal", tb->err_cycles[COND_done]);
 }
@@ -1751,10 +1663,14 @@ void tb_tx_frontend_8N2(TB_Tx_frontend * tb) {
   
   tb->tick();
 
+  //=================================
+  //      Tick (2)
+  
+  tb->tick();
+
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
   tb->check(COND_output, (core->uart_tx_o == 0));
   tb->check(COND_done,   (core->done_o == 0));
 
@@ -1764,7 +1680,7 @@ void tb_tx_frontend_8N2(TB_Tx_frontend * tb) {
   core->transmit_i = 0;
 
   //=================================
-  //      Tick (2-10)
+  //      Tick (3-11)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -1772,13 +1688,12 @@ void tb_tx_frontend_8N2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (11-20)
+  //      Tick (12-21)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -1786,13 +1701,12 @@ void tb_tx_frontend_8N2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (21-29)
+  //      Tick (22-30)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -1800,13 +1714,12 @@ void tb_tx_frontend_8N2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (30-39)
+  //      Tick (31-40)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -1814,13 +1727,12 @@ void tb_tx_frontend_8N2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (40-49)
+  //      Tick (41-50)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -1828,13 +1740,12 @@ void tb_tx_frontend_8N2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (50-58)
+  //      Tick (51-59)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -1842,13 +1753,12 @@ void tb_tx_frontend_8N2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (59-68)
+  //      Tick (60-69)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -1856,13 +1766,12 @@ void tb_tx_frontend_8N2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (69-77)
+  //      Tick (70-78)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -1870,13 +1779,12 @@ void tb_tx_frontend_8N2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (78-87)
+  //      Tick (79-88)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -1884,13 +1792,12 @@ void tb_tx_frontend_8N2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (88-96)
+  //      Tick (89-97)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -1898,21 +1805,19 @@ void tb_tx_frontend_8N2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (97-106)
+  //      Tick (98-106)
   
-  for(size_t i = 0; i < 10; i++) {
+  for(size_t i = 0; i < 9; i++) {
     tb->tick();
 
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
@@ -1925,7 +1830,7 @@ void tb_tx_frontend_8N2(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
+  tb->check(COND_output, (core->uart_tx_o == 1));
   tb->check(COND_done,   (core->done_o == 1));
 
   //=================================
@@ -1936,21 +1841,16 @@ void tb_tx_frontend_8N2(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
   tb->check(COND_done,   (core->done_o == 0));
 
   //`````````````````````````````````
   //      Formal Checks 
   
   CHECK("tb_tx_frontend.8N2.01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
-
-  CHECK("tb_tx_frontend.8N2.02",
       tb->conditions[COND_output],
       "Failed to implement the output signal", tb->err_cycles[COND_output]);
 
-  CHECK("tb_tx_frontend.8N2.03",
+  CHECK("tb_tx_frontend.8N2.02",
       tb->conditions[COND_done],
       "Failed to implement the done signal", tb->err_cycles[COND_done]);
 }
@@ -1981,10 +1881,14 @@ void tb_tx_frontend_8E1(TB_Tx_frontend * tb) {
   
   tb->tick();
 
+  //=================================
+  //      Tick (2)
+  
+  tb->tick();
+
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
   tb->check(COND_output, (core->uart_tx_o == 0));
   tb->check(COND_done,   (core->done_o == 0));
 
@@ -1994,7 +1898,7 @@ void tb_tx_frontend_8E1(TB_Tx_frontend * tb) {
   core->transmit_i = 0;
 
   //=================================
-  //      Tick (2-10)
+  //      Tick (3-11)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -2002,13 +1906,12 @@ void tb_tx_frontend_8E1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (11-20)
+  //      Tick (12-21)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -2016,13 +1919,12 @@ void tb_tx_frontend_8E1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (21-29)
+  //      Tick (22-30)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -2030,13 +1932,12 @@ void tb_tx_frontend_8E1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (30-39)
+  //      Tick (31-40)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -2044,13 +1945,12 @@ void tb_tx_frontend_8E1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (40-49)
+  //      Tick (41-50)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -2058,13 +1958,12 @@ void tb_tx_frontend_8E1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (50-58)
+  //      Tick (51-59)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -2072,13 +1971,12 @@ void tb_tx_frontend_8E1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (59-68)
+  //      Tick (60-69)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -2086,13 +1984,12 @@ void tb_tx_frontend_8E1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (69-77)
+  //      Tick (70-78)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -2100,13 +1997,12 @@ void tb_tx_frontend_8E1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (78-87)
+  //      Tick (79-88)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -2114,13 +2010,12 @@ void tb_tx_frontend_8E1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (88-96)
+  //      Tick (89-97)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -2128,21 +2023,19 @@ void tb_tx_frontend_8E1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_PARITY));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (97-106)
+  //      Tick (98-106)
   
-  for(size_t i = 0; i < 10; i++) {
+  for(size_t i = 0; i < 9; i++) {
     tb->tick();
 
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
@@ -2155,33 +2048,27 @@ void tb_tx_frontend_8E1(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
+  tb->check(COND_output, (core->uart_tx_o == 1));
   tb->check(COND_done,   (core->done_o == 1));
 
   //=================================
-  //      Tick (108)
+  //      Tick (109)
   
   tb->tick();
 
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
   tb->check(COND_done,   (core->done_o == 0));
 
-
   //`````````````````````````````````
   //      Formal Checks 
   
   CHECK("tb_tx_frontend.8E1.01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
-
-  CHECK("tb_tx_frontend.8E1.02",
       tb->conditions[COND_output],
       "Failed to implement the output signal", tb->err_cycles[COND_output]);
 
-  CHECK("tb_tx_frontend.8E1.03",
+  CHECK("tb_tx_frontend.8E1.02",
       tb->conditions[COND_done],
       "Failed to implement the done signal", tb->err_cycles[COND_done]);
 }
@@ -2212,10 +2099,14 @@ void tb_tx_frontend_8E2(TB_Tx_frontend * tb) {
   
   tb->tick();
 
+  //=================================
+  //      Tick (2)
+  
+  tb->tick();
+
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
   tb->check(COND_output, (core->uart_tx_o == 0));
   tb->check(COND_done,   (core->done_o == 0));
 
@@ -2225,7 +2116,7 @@ void tb_tx_frontend_8E2(TB_Tx_frontend * tb) {
   core->transmit_i = 0;
 
   //=================================
-  //      Tick (2-10)
+  //      Tick (3-11)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -2233,13 +2124,12 @@ void tb_tx_frontend_8E2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (11-20)
+  //      Tick (12-21)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -2247,13 +2137,12 @@ void tb_tx_frontend_8E2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (21-29)
+  //      Tick (22-30)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -2261,13 +2150,12 @@ void tb_tx_frontend_8E2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (30-39)
+  //      Tick (31-40)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -2275,13 +2163,12 @@ void tb_tx_frontend_8E2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (40-49)
+  //      Tick (41-50)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -2289,13 +2176,12 @@ void tb_tx_frontend_8E2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (50-58)
+  //      Tick (51-59)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -2303,13 +2189,12 @@ void tb_tx_frontend_8E2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (59-68)
+  //      Tick (60-69)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -2317,13 +2202,12 @@ void tb_tx_frontend_8E2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (69-77)
+  //      Tick (70-78)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -2331,13 +2215,12 @@ void tb_tx_frontend_8E2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (78-87)
+  //      Tick (79-88)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -2345,13 +2228,12 @@ void tb_tx_frontend_8E2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (88-96)
+  //      Tick (89-97)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -2359,13 +2241,12 @@ void tb_tx_frontend_8E2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_PARITY));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (97-106)
+  //      Tick (98-107)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -2373,21 +2254,19 @@ void tb_tx_frontend_8E2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (107-116)
+  //      Tick (108-116)
   
-  for(size_t i = 0; i < 10; i++) {
+  for(size_t i = 0; i < 9; i++) {
     tb->tick();
 
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
@@ -2400,7 +2279,7 @@ void tb_tx_frontend_8E2(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
+  tb->check(COND_output, (core->uart_tx_o == 1));
   tb->check(COND_done,   (core->done_o == 1));
 
   //=================================
@@ -2411,21 +2290,16 @@ void tb_tx_frontend_8E2(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
   tb->check(COND_done,   (core->done_o == 0));
 
   //`````````````````````````````````
   //      Formal Checks 
   
   CHECK("tb_tx_frontend.8E2.01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
-
-  CHECK("tb_tx_frontend.8E2.02",
       tb->conditions[COND_output],
       "Failed to implement the output signal", tb->err_cycles[COND_output]);
 
-  CHECK("tb_tx_frontend.8E2.03",
+  CHECK("tb_tx_frontend.8E2.02",
       tb->conditions[COND_done],
       "Failed to implement the done signal", tb->err_cycles[COND_done]);
 }
@@ -2456,10 +2330,14 @@ void tb_tx_frontend_8O1(TB_Tx_frontend * tb) {
   
   tb->tick();
 
+  //=================================
+  //      Tick (2)
+  
+  tb->tick();
+
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
   tb->check(COND_output, (core->uart_tx_o == 0));
   tb->check(COND_done,   (core->done_o == 0));
 
@@ -2469,7 +2347,7 @@ void tb_tx_frontend_8O1(TB_Tx_frontend * tb) {
   core->transmit_i = 0;
 
   //=================================
-  //      Tick (2-10)
+  //      Tick (3-11)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -2477,13 +2355,12 @@ void tb_tx_frontend_8O1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (11-20)
+  //      Tick (12-21)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -2491,13 +2368,12 @@ void tb_tx_frontend_8O1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (21-29)
+  //      Tick (22-30)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -2505,13 +2381,12 @@ void tb_tx_frontend_8O1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (30-39)
+  //      Tick (31-40)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -2519,13 +2394,12 @@ void tb_tx_frontend_8O1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (40-49)
+  //      Tick (41-50)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -2533,13 +2407,12 @@ void tb_tx_frontend_8O1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (50-58)
+  //      Tick (51-59)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -2547,13 +2420,12 @@ void tb_tx_frontend_8O1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (59-68)
+  //      Tick (60-69)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -2561,13 +2433,12 @@ void tb_tx_frontend_8O1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (69-77)
+  //      Tick (70-78)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -2575,13 +2446,12 @@ void tb_tx_frontend_8O1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (78-87)
+  //      Tick (79-88)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -2589,13 +2459,12 @@ void tb_tx_frontend_8O1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (88-96)
+  //      Tick (89-97)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -2603,21 +2472,19 @@ void tb_tx_frontend_8O1(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_PARITY));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (97-106)
+  //      Tick (98-106)
   
-  for(size_t i = 0; i < 10; i++) {
+  for(size_t i = 0; i < 9; i++) {
     tb->tick();
 
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
@@ -2630,7 +2497,7 @@ void tb_tx_frontend_8O1(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
+  tb->check(COND_output, (core->uart_tx_o == 1));
   tb->check(COND_done,   (core->done_o == 1));
 
   //=================================
@@ -2641,21 +2508,16 @@ void tb_tx_frontend_8O1(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
   tb->check(COND_done,   (core->done_o == 0));
 
   //`````````````````````````````````
   //      Formal Checks 
   
   CHECK("tb_tx_frontend.8O1.01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
-
-  CHECK("tb_tx_frontend.8O1.02",
       tb->conditions[COND_output],
       "Failed to implement the output signal", tb->err_cycles[COND_output]);
 
-  CHECK("tb_tx_frontend.8O1.03",
+  CHECK("tb_tx_frontend.8O1.02",
       tb->conditions[COND_done],
       "Failed to implement the done signal", tb->err_cycles[COND_done]);
 }
@@ -2686,10 +2548,14 @@ void tb_tx_frontend_8O2(TB_Tx_frontend * tb) {
   
   tb->tick();
 
+  //=================================
+  //      Tick (2)
+  
+  tb->tick();
+
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
   tb->check(COND_output, (core->uart_tx_o == 0));
   tb->check(COND_done,   (core->done_o == 0));
 
@@ -2699,7 +2565,7 @@ void tb_tx_frontend_8O2(TB_Tx_frontend * tb) {
   core->transmit_i = 0;
 
   //=================================
-  //      Tick (2-10)
+  //      Tick (3-11)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -2707,13 +2573,12 @@ void tb_tx_frontend_8O2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_START));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (11-20)
+  //      Tick (12-21)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -2721,13 +2586,12 @@ void tb_tx_frontend_8O2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (21-29)
+  //      Tick (22-30)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -2735,13 +2599,12 @@ void tb_tx_frontend_8O2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (30-39)
+  //      Tick (31-40)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -2749,13 +2612,12 @@ void tb_tx_frontend_8O2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (40-49)
+  //      Tick (41-50)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -2763,13 +2625,12 @@ void tb_tx_frontend_8O2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (50-58)
+  //      Tick (51-59)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -2777,13 +2638,12 @@ void tb_tx_frontend_8O2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (59-68)
+  //      Tick (60-69)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -2791,13 +2651,12 @@ void tb_tx_frontend_8O2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (69-77)
+  //      Tick (70-78)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -2805,13 +2664,12 @@ void tb_tx_frontend_8O2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (78-87)
+  //      Tick (79-88)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -2819,13 +2677,12 @@ void tb_tx_frontend_8O2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_DATA));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (88-96)
+  //      Tick (89-97)
   
   for(size_t i = 0; i < 9; i++) {
     tb->tick();
@@ -2833,13 +2690,12 @@ void tb_tx_frontend_8O2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_PARITY));
     tb->check(COND_output, (core->uart_tx_o == 0));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (97-106)
+  //      Tick (99-107)
   
   for(size_t i = 0; i < 10; i++) {
     tb->tick();
@@ -2847,21 +2703,19 @@ void tb_tx_frontend_8O2(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
 
   //=================================
-  //      Tick (107-116)
+  //      Tick (108-116)
   
-  for(size_t i = 0; i < 10; i++) {
+  for(size_t i = 0; i < 9; i++) {
     tb->tick();
 
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_STOP));
     tb->check(COND_output, (core->uart_tx_o == 1));
     tb->check(COND_done,   (core->done_o == 0));
   }
@@ -2874,7 +2728,7 @@ void tb_tx_frontend_8O2(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
+  tb->check(COND_output, (core->uart_tx_o == 1));
   tb->check(COND_done,   (core->done_o == 1));
 
   //=================================
@@ -2885,21 +2739,16 @@ void tb_tx_frontend_8O2(TB_Tx_frontend * tb) {
   //`````````````````````````````````
   //      Checks 
   
-  tb->check(COND_state,  (core->tb_tx_frontend->dut->state_q == S_IDLE));
   tb->check(COND_done,   (core->done_o == 0));
 
   //`````````````````````````````````
   //      Formal Checks 
   
   CHECK("tb_tx_frontend.8O2.01",
-      tb->conditions[COND_state],
-      "Failed to implement the state machine", tb->err_cycles[COND_state]);
-
-  CHECK("tb_tx_frontend.8O2.02",
       tb->conditions[COND_output],
       "Failed to implement the output signal", tb->err_cycles[COND_output]);
 
-  CHECK("tb_tx_frontend.8O2.03",
+  CHECK("tb_tx_frontend.8O2.02",
       tb->conditions[COND_done],
       "Failed to implement the done signal", tb->err_cycles[COND_done]);
 }
@@ -2931,7 +2780,7 @@ void tb_tx_frontend_baudrate(TB_Tx_frontend * tb) {
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_baudrate,  (precision < 0.02));
+    tb->check(COND_baudrate,  (precision < 0.01));
   }
 
   //`````````````````````````````````

From e329cb08990d91f770c27eb0c8b84e0620cf55f3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Cl=C3=A9ment=20Chaine?= <clement.chaine25@gmail.com>
Date: Sat, 27 Dec 2025 17:59:57 +0100
Subject: [PATCH 13/15] Fix false ok in baudrate tests

---
 tests/benches/tx_frontend/tb_tx_frontend.cpp | 28 +++++++++++++++-----
 1 file changed, 22 insertions(+), 6 deletions(-)

diff --git a/tests/benches/tx_frontend/tb_tx_frontend.cpp b/tests/benches/tx_frontend/tb_tx_frontend.cpp
index 2ceedb0..cd94c7c 100644
--- a/tests/benches/tx_frontend/tb_tx_frontend.cpp
+++ b/tests/benches/tx_frontend/tb_tx_frontend.cpp
@@ -89,9 +89,15 @@ class TB_Tx_frontend : public Testbench<Vtb_tx_frontend> {
   }
 
   float get_generated_baudrate(uint32_t baudrate) {
-    this->reset();
+    this->_nop();
+
+    this->core->rst_i = 1;
+    for(int i = 0; i < 5; i++) {
+      this->tick();
+    }
+    this->core->rst_i = 0;
 
-    core->cr_acc_incr_i = ((double)baudrate * (1 << 16)) / 24000000;
+    core->cr_acc_incr_i = ((double)baudrate * (1 << 16)) / 60000000;
     core->cr_ds_i = 1;
     core->cr_p_i = 1;
     core->cr_s_i = 1;
@@ -115,7 +121,7 @@ class TB_Tx_frontend : public Testbench<Vtb_tx_frontend> {
     }
 
     // Compute the baudrate
-    float duration = (counter / 24000000.0);
+    float duration = (counter / 60000000.0);
     float baud_period = duration / 12;
     float generated_baudrate = (1.0 / baud_period);
     return generated_baudrate;
@@ -2777,10 +2783,20 @@ void tb_tx_frontend_baudrate(TB_Tx_frontend * tb) {
     float generated_baudrate = tb->get_generated_baudrate(baudrates[i]);
     float precision = (1.0 - (generated_baudrate / baudrates[i]));
 
+    if(tb->debug_log) {
+      printf("Baudrate: %d, acc: %d, precision: %f -> ", baudrates[i], core->cr_acc_incr_i, precision);
+
+      if(precision >= 0.02) {
+        printf("BAD\n");
+      } else {
+        printf("OK\n");
+      }
+    }
+
     //`````````````````````````````````
     //      Checks 
     
-    tb->check(COND_baudrate,  (precision < 0.01));
+    tb->check(COND_baudrate,  (precision < 0.02));
   }
 
   //`````````````````````````````````
@@ -2803,8 +2819,8 @@ int main(int argc, char ** argv, char ** env) {
   tb->set_debug_log(verbose);
   tb->init_conditions(__CondIdEnd);
 
-  // 24MHz
-  tb->clk_period_in_ps = 41667;
+  // 60MHz
+  tb->clk_period_in_ps = 16667;
 
   /************************************************************/
 

From b2fe25504558ca675f6e4e0826345a7f2c1da0d1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Cl=C3=A9ment=20Chaine?= <clement.chaine25@gmail.com>
Date: Sun, 28 Dec 2025 17:28:08 +0100
Subject: [PATCH 14/15] Fix testbench frequency to 78MHz

---
 tests/benches/tx_frontend/tb_tx_frontend.cpp | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/tests/benches/tx_frontend/tb_tx_frontend.cpp b/tests/benches/tx_frontend/tb_tx_frontend.cpp
index cd94c7c..cbdf71f 100644
--- a/tests/benches/tx_frontend/tb_tx_frontend.cpp
+++ b/tests/benches/tx_frontend/tb_tx_frontend.cpp
@@ -97,7 +97,7 @@ class TB_Tx_frontend : public Testbench<Vtb_tx_frontend> {
     }
     this->core->rst_i = 0;
 
-    core->cr_acc_incr_i = ((double)baudrate * (1 << 16)) / 60000000;
+    core->cr_acc_incr_i = ((double)baudrate * (1 << 16)) / 78000000;
     core->cr_ds_i = 1;
     core->cr_p_i = 1;
     core->cr_s_i = 1;
@@ -121,7 +121,7 @@ class TB_Tx_frontend : public Testbench<Vtb_tx_frontend> {
     }
 
     // Compute the baudrate
-    float duration = (counter / 60000000.0);
+    float duration = (counter / 78000000.0);
     float baud_period = duration / 12;
     float generated_baudrate = (1.0 / baud_period);
     return generated_baudrate;
@@ -2819,8 +2819,8 @@ int main(int argc, char ** argv, char ** env) {
   tb->set_debug_log(verbose);
   tb->init_conditions(__CondIdEnd);
 
-  // 60MHz
-  tb->clk_period_in_ps = 16667;
+  // 78MHz
+  tb->clk_period_in_ps = 12821;
 
   /************************************************************/
 

From 2da1e8b004db88c528555fcbf96a80530e787d09 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Cl=C3=A9ment=20Chaine?= <clement.chaine25@gmail.com>
Date: Sat, 3 Jan 2026 11:52:57 +0100
Subject: [PATCH 15/15] Update to released dependencies

---
 CMakeLists.txt                   | 10 +++---
 config/traceability-matrix.csv   | 37 +++++++++------------
 docs/src/spec/3_requirements.rst | 56 +-------------------------------
 3 files changed, 22 insertions(+), 81 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 5483f61..8872628 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -48,24 +48,24 @@ add_dependency(
 
 add_dependency(
   GIT ecap5/verilator-cmake
-  TAG release/v1.1.0)
+  TAG tags/v1.1.0)
 
 add_dependency(
   GIT ecap5/ecap5-treq
-  TAG release/v3.0.0
+  TAG tags/v3.0.0
   BINARY ecap5-treq)
 
 add_dependency(
   GIT ecap5/oss-cad-suite-cmake
-  TAG release/v2.0.0)
+  TAG tags/v2.0.0)
 
 add_dependency(
   GIT ecap5/ecap5-dtestlib
-  TAG release/v1.1.0)
+  TAG tags/v1.1.0)
 
 add_dependency(
   GIT ecap5/ecap5-dwbmmsc
-  TAG release/v1.0.0)
+  TAG tags/v1.0.0-beta1)
 
 # Define an interface library
 add_library(ecap5_dwbuart INTERFACE)
diff --git a/config/traceability-matrix.csv b/config/traceability-matrix.csv
index 5d505ba..5585f47 100644
--- a/config/traceability-matrix.csv
+++ b/config/traceability-matrix.csv
@@ -16,13 +16,19 @@ tb_ecap5_dwbuart.read_rxdr.03;F_REGISTERS_01;F_READ_01;F_RECEIVE_02;F_RECEIVE_03
 tb_ecap5_dwbuart.rxoe.01
 tb_ecap5_dwbuart.rxoe.02
 tb_ecap5_dwbuart.rxoe.03;F_REGISTERS_01;F_READ_02;F_RECEIVE_ERROR_03
-tb_ecap5_dwbuart.pe.01
-tb_ecap5_dwbuart.pe.02;F_REGISTERS_01;F_READ_02;F_RECEIVE_ERROR_01
 tb_ecap5_dwbuart.fe.01
 tb_ecap5_dwbuart.fe.02;F_REGISTERS_01;F_READ_02;F_RECEIVE_ERROR_02
-tb_ecap5_dwbuart.full_duplex.01;F_UART_04
-tb_ecap5_dwbuart.full_duplex.02;F_UART_04
-tb_ecap5_dwbuart.full_duplex.03;F_REGISTERS_01;F_UART_04
+tb_ecap5_dwbuart.pe.01
+tb_ecap5_dwbuart.pe.02;F_REGISTERS_01;F_READ_02;F_RECEIVE_ERROR_01
+tb_ecap5_dwbuart.error_retention.01
+tb_ecap5_dwbuart.error_retention.02
+tb_ecap5_dwbuart.race_sr.01
+tb_ecap5_dwbuart.race_sr.02
+tb_ecap5_dwbuart.race_txdr.01
+tb_ecap5_dwbuart.race_txdr.02
+tb_ecap5_dwbuart.race_txdr.03
+tb_ecap5_dwbuart.race_rxdr.01
+tb_ecap5_dwbuart.race_rxdr.02
 tb_rx_frontend.idle.01
 tb_rx_frontend.idle.02
 tb_rx_frontend.valid.7N1_01
@@ -73,10 +79,6 @@ tb_rx_frontend.valid.8O2_01
 tb_rx_frontend.valid.8O2_02;F_UART_01;F_UART_02;F_RECEIVE_01
 tb_rx_frontend.valid.8O2_03
 tb_rx_frontend.valid.8O2_04;F_UART_02;F_UART_03;F_RECEIVE_02
-tb_rx_frontend.baudrate.01
-tb_rx_frontend.baudrate.02;F_UART_01;F_UART_02;F_RECEIVE_01
-tb_rx_frontend.baudrate.03
-tb_rx_frontend.baudrate.04;F_UART_02;F_UART_03;F_RECEIVE_02
 tb_rx_frontend.parity.EVEN_01;F_RECEIVE_ERROR_01
 tb_rx_frontend.parity.EVEN_02
 tb_rx_frontend.parity.ODD_01;F_RECEIVE_ERROR_01
@@ -84,9 +86,12 @@ tb_rx_frontend.parity.ODD_02
 tb_rx_frontend.framing.01
 tb_rx_frontend.framing.02;F_RECEIVE_ERROR_02
 tb_rx_frontend.framing.03
+tb_rx_frontend.baudrate.01;U_BAUD_RATE_02
+tb_rx_frontend.baudrate.02;F_UART_01;F_UART_02;F_RECEIVE_01;U_BAUD_RATE_02
+tb_rx_frontend.baudrate.03;U_BAUD_RATE_02
+tb_rx_frontend.baudrate.04;F_UART_02;F_UART_03;F_RECEIVE_02;U_BAUD_RATE_02
 tb_tx_frontend.idle.01
 tb_tx_frontend.idle.02
-tb_tx_frontend.idle.03
 tb_tx_frontend.7N1.01;F_UART_01;F_UART_02;F_TRANSMIT_01
 tb_tx_frontend.7N1.02;F_UART_02;F_UART_03;F_TRANSMIT_01
 tb_tx_frontend.7N2.01;F_UART_01;F_UART_02;F_TRANSMIT_01
@@ -111,14 +116,4 @@ tb_tx_frontend.8O1.01;F_UART_01;F_UART_02;F_TRANSMIT_01
 tb_tx_frontend.8O1.02;F_UART_02;F_UART_03;F_TRANSMIT_01
 tb_tx_frontend.8O2.01;F_UART_01;F_UART_02;F_TRANSMIT_01
 tb_tx_frontend.8O2.02;F_UART_02;F_UART_03;F_TRANSMIT_01
-tb_tx_frontend.baudrate.01
-tb_tx_frontend.baudrate.02;F_UART_01;F_UART_02;F_TRANSMIT_01
-tb_tx_frontend.baudrate.03;F_UART_02;F_UART_03;F_TRANSMIT_01
-tb_wb_interface.reset.01;F_WISHBONE_RESET_01
-tb_wb_interface.reset.02;F_WISHBONE_RESET_02
-tb_wb_interface.read.01;F_WISHBONE_READ_CYCLE_01
-tb_wb_interface.read.02;F_WISHBONE_TRANSFER_CYCLE_01;F_WISHBONE_HANDSHAKE_01;F_WISHBONE_READ_CYCLE_01
-tb_wb_interface.write.01;F_WISHBONE_WRITE_CYCLE_01
-tb_wb_interface.write.02;F_WISHBONE_WRITE_CYCLE_01
-__UNTRACEABLE__;F_WISHBONE_DATASHEET_01;This requirement is covered by the hdl code.
-__UNTRACEABLE__;F_WISHBONE_TIMING_01;This requirement is covered by the hdl code.
+tb_tx_frontend.baudrate.01;U_BAUD_RATE_02
diff --git a/docs/src/spec/3_requirements.rst b/docs/src/spec/3_requirements.rst
index fee0d35..67ba7b6 100644
--- a/docs/src/spec/3_requirements.rst
+++ b/docs/src/spec/3_requirements.rst
@@ -107,61 +107,7 @@ Functional Requirements
 Memory interface
 ^^^^^^^^^^^^^^^^
 
-Wishbone protocol
-`````````````````
-
-The following requirements are extracted from the Wishbone specification.
-
-.. requirement:: F_WISHBONE_DATASHEET_01
-  :derivedfrom: U_MEMORY_INTERFACE_01
-
-  The memory interface shall comply with the Wishbone Datasheet provided in section 2.1.
-
-.. requirement:: F_WISHBONE_RESET_01
-  :derivedfrom: U_MEMORY_INTERFACE_01
-
-  The memory interface shall initialize itself at the rising edge of clk_i following the assertion of rst_i.
-
-.. requirement:: F_WISHBONE_RESET_02
-  :derivedfrom: U_MEMORY_INTERFACE_01
-
-  The memory interface shall stay in the initialization state until the rising edge of clk_i following the deassertion of rst_i.
-
-.. requirement:: F_WISHBONE_TRANSFER_CYCLE_01
-  :derivedfrom: U_MEMORY_INTERFACE_01
-
-  The memory interface shall only respond to transfer cycles when wb_cyc_i is asserted.
-
-.. requirement:: F_WISHBONE_HANDSHAKE_01
-  :derivedfrom: U_MEMORY_INTERFACE_01
-
-  The memory interface shall assert the wb_ack_o signal in response to the logical AND of wb_cyc_i and wb_stb_i.
-
-.. requirement:: F_WISHBONE_READ_CYCLE_01
-  :derivedfrom: U_MEMORY_INTERFACE_01
-
-  The memory interface shall conform to the READ cycle detailed in the figure below.
-
-.. figure:: ../assets/wishbone-read.svg
-   :align: center
-   
-   Timing diagram of the wishbone read cycle
-
-.. requirement:: F_WISHBONE_WRITE_CYCLE_01
-  :derivedfrom: U_MEMORY_INTERFACE_01
-
-  The memory interface shall conform to the WRITE cycle detailed in figure below.
-
-.. figure:: ../assets/wishbone-write.svg
-   :align: center
-   
-   Timing diagram of the wishbone write cycle
-
-.. requirement:: F_WISHBONE_TIMING_01
-  :rationale: As long as the memory interface is designed within the clock domain of clk_i, the requirement will be satisfied by using the place and route tool.
-  :derivedfrom: U_MEMORY_INTERFACE_01
-
-  The clock input clk_i shall coordinate all activites for the internal logic within the memory interface. All output signals of the memory interface shall be registered at the rising edge of clk_i. All input signals of the memory interface shall be stable before the rising edge of clk_i.
+.. note:: The wishbone protocol is not specified here as this module is expected to use ECAP5-DWBMMSC as its wishbone interface.
 
 Memory-mapped registers
 ```````````````````````