From e359a7a7489ed312da998e01fb44298e7c982da8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20Chaine?= Date: Sat, 6 Dec 2025 19:21:17 +0100 Subject: [PATCH 1/2] Use verilator-cmake v1.1.0 --- CMakeLists.txt | 2 +- tests/CMakeLists.txt | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 40ea049..5483f61 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -48,7 +48,7 @@ add_dependency( add_dependency( GIT ecap5/verilator-cmake - TAG tags/v1.0.1) + TAG release/v1.1.0) add_dependency( GIT ecap5/ecap5-treq diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index 370b5f0..06137aa 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -29,7 +29,7 @@ set(TESTDATA_DIR ${CMAKE_CURRENT_BINARY_DIR}/) # Lint add_lint_target( TARGET lint - LIB ecap5_dwbmmsc + LIB ecap5_dwbuart ) # Add testbenches From e54ba90e7035ff7f306d899a70be49bea7e9a6df Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20Chaine?= Date: Sat, 6 Dec 2025 19:30:48 +0100 Subject: [PATCH 2/2] Fix linting issues --- src/ecap5_dwbuart.sv | 26 +++++++++++++------------- src/rx_frontend.sv | 6 +++--- src/tx_frontend.sv | 4 ++-- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/src/ecap5_dwbuart.sv b/src/ecap5_dwbuart.sv index 0fdf5e6..404fcbd 100644 --- a/src/ecap5_dwbuart.sv +++ b/src/ecap5_dwbuart.sv @@ -21,21 +21,21 @@ */ module ecap5_dwbuart #( - localparam UART_SR = 0, - localparam UART_CR = 1, - localparam UART_RXDR = 2, - localparam UART_TXDR = 3, + localparam logic[2:0] UART_SR = 0, + localparam logic[2:0] UART_CR = 1, + localparam logic[2:0] UART_RXDR = 2, + localparam logic[2:0] UART_TXDR = 3, // The minimum frame size is : // - 7 data bits // - 1 stop bit - localparam MIN_FRAME_SIZE = 8, + localparam logic[3:0] MIN_FRAME_SIZE = 8, // The maximum frame size is : // - 8 data bits // - 1 parity bit // - 2 stop bit - localparam MAX_FRAME_SIZE = 11 + localparam logic[3:0] MAX_FRAME_SIZE = 11 )( input logic clk_i, input logic rst_i, @@ -169,7 +169,7 @@ always_comb begin : register_access // Set the data output for read requests mem_read_data_d = 0; - case(mem_addr[7:2]) + case(mem_addr[4:2]) UART_SR: mem_read_data_d = {27'b0, sr_pe_q, sr_fe_q, sr_rxoe_q, sr_txe_q, sr_rxne_q}; UART_CR: mem_read_data_d = {cr_acc_incr_q, 12'b0, cr_ds_q, cr_s_q, cr_p_q}; UART_RXDR: mem_read_data_d = {24'b0, rxdr_rxd_q}; @@ -178,7 +178,7 @@ always_comb begin : register_access // Set the register data for write requests if(mem_write) begin - case(mem_addr[7:2]) + case(mem_addr[4:2]) UART_CR: begin cr_acc_incr_d = mem_write_data[31:16]; cr_ds_d = mem_write_data[3]; @@ -193,7 +193,7 @@ always_comb begin : register_access end // Priority to the memory request - if(mem_write && (mem_addr[7:2] == UART_TXDR)) begin + if(mem_write && (mem_addr[4:2] == UART_TXDR)) begin sr_txe_d = 0; end else if (tx_done) begin sr_txe_d = 1; @@ -214,12 +214,12 @@ always_comb begin : register_access end // When the memory request occurs but no data was received // we clear the previously received data - end else if(mem_read && mem_addr[7:2] == UART_RXDR) begin + end else if(mem_read && mem_addr[4:2] == UART_RXDR) begin rxdr_rxd_d = '0; sr_rxne_d = 0; // When the memory request occurs but no data was received // we clear the errors - end else if(mem_read && mem_addr[7:2] == UART_SR) begin + end else if(mem_read && mem_addr[4:2] == UART_SR) begin sr_pe_d = 0; sr_fe_d = 0; sr_rxoe_d = 0; @@ -228,10 +228,10 @@ end always_comb begin : frontend_interface // Reset the frontends after either a reset or a write to UART_CR - frontend_rst = rst_i || (mem_write && mem_addr[7:2] == UART_CR); + frontend_rst = rst_i || (mem_write && mem_addr[4:2] == UART_CR); // Transmit after a write to UART_TXDR - tx_transmit_d = mem_write && (mem_addr[7:2] == UART_TXDR); + tx_transmit_d = mem_write && (mem_addr[4:2] == UART_TXDR); end always_ff @(posedge clk_i) begin diff --git a/src/rx_frontend.sv b/src/rx_frontend.sv index a0d0b19..b4e60df 100644 --- a/src/rx_frontend.sv +++ b/src/rx_frontend.sv @@ -21,8 +21,8 @@ */ module rx_frontend #( - parameter MIN_FRAME_SIZE = 8, - parameter MAX_FRAME_SIZE = 11 + parameter logic[3:0] MIN_FRAME_SIZE = 8, + parameter logic[3:0] MAX_FRAME_SIZE = 11 )( input logic clk_i, input logic rst_i, @@ -54,7 +54,7 @@ state_t state_d, state_q; logic uart_rx_q, uart_rx_qq, uart_rx_qqq; logic[16:0] baud_acc_d, baud_acc_q; -logic baud_acc_half_overflow, baud_acc_overflow;; +logic baud_acc_half_overflow, baud_acc_overflow; logic[MAX_FRAME_SIZE:0] frame_bit_cnt_d, frame_bit_cnt_q; diff --git a/src/tx_frontend.sv b/src/tx_frontend.sv index 74794ef..0692614 100644 --- a/src/tx_frontend.sv +++ b/src/tx_frontend.sv @@ -21,8 +21,8 @@ */ module tx_frontend #( - parameter MIN_FRAME_SIZE = 8, - parameter MAX_FRAME_SIZE = 11 + parameter logic[3:0] MIN_FRAME_SIZE = 8, + parameter logic[3:0] MAX_FRAME_SIZE = 11 )( input logic clk_i, input logic rst_i,