|
| 1 | +# OpenBMC Lab Assembly Guide for ASRock Turin |
| 2 | + |
| 3 | +## Introduction |
| 4 | + |
| 5 | +This document describes platform-specific details for assembling an |
| 6 | +[ASRock Rack TURIND8UD-2T/X550](https://www.asrockrack.com/general/productdetail.asp?Model=TURIND8UD-2T/X550#Specifications) |
| 7 | +testing stand. Use this document as reference while going through |
| 8 | +[Generic Testing Stand Setup](../../unified-test-documentation/generic-testing-stand-setup.md) |
| 9 | + |
| 10 | +## Prerequisites |
| 11 | + |
| 12 | +The below table contains information about all elements which are needed to |
| 13 | +create the testing stand. Most of the hardware matches the platform's main |
| 14 | +components - refer to the |
| 15 | +[hardware configuration matrix](../../variants/asrock_turind8ud/hardware-matrix.md#main-components) |
| 16 | +for the CPU, RAM, case, power supply, and so on. |
| 17 | + |
| 18 | +- ASRock Rack TURIND8UD-2T/X550 platform |
| 19 | +- [RTE v1.1.0](https://shop.3mdeb.com/shop/open-source-hardware/open-source-hardware-3mdeb/rte/) |
| 20 | +- RTE SPI extender HAT (exposes `SPI_1` and `SPI_2` headers) |
| 21 | +- NOUS A1T smart outlet |
| 22 | +- IDC to RS232 adapter |
| 23 | +- RS232 null modem cable |
| 24 | +- SPI flash TPM adapter set, one for the motherboard `TPM_BIOS_PH_1` header and |
| 25 | + one for the SPI extender HAT |
| 26 | +- matching IDC or FPC cable around 30 cm long (for the host SPI flash), |
| 27 | + depending on adapter used in previous point |
| 28 | + * FPC: pitch 1 mm, 13 conductors, same side contacts |
| 29 | + * IDC: pitch: 2.54 mm, 14 conductors |
| 30 | +- 3x 2.54 mm female to female jumper wire cables |
| 31 | +- 2x5 1.27mm pitch IDC connector to individual 2.54mm female connector |
| 32 | + cables (for the BMC SPI flash) |
| 33 | +- 3D printed RTE mount (modular base with a stackable RTE base) |
| 34 | +- 4x M3 6mm screws with nuts (to join the 3D printed parts) |
| 35 | +- 7x M3 6mm screws (3 to fasten the RTE to the RTE base, 4 to fasten the base to |
| 36 | + the PC case) |
| 37 | + |
| 38 | +## RTE mount |
| 39 | + |
| 40 | +The RTE sits on a 3D printed mount that screws into the bottom of the PC case, |
| 41 | +reusing the case's fan or SSD mounting holes. The mount is modular: printed |
| 42 | +parts stack on top of the base and screw together, and the RTE fastens to a |
| 43 | +printed RTE base on the stack. |
| 44 | + |
| 45 | +1. Join the 3D printed parts. Each edge is fixed with an M3 6mm screw and nut, |
| 46 | + four pairs in total (one per edge): |
| 47 | + |
| 48 | +  |
| 49 | + |
| 50 | +1. Fasten the RTE to the RTE base with 3 M3 6mm screws: |
| 51 | + |
| 52 | +  |
| 53 | + |
| 54 | +1. Stack the SPI extender HAT (RTE SPI mux) on top of the RTE: |
| 55 | + |
| 56 | +  |
| 57 | + |
| 58 | +1. Screw the assembled base into the bottom of the PC case with 4 M3 6mm screws, |
| 59 | + using the case's fan or SSD mounting holes. The bare base is shown below to |
| 60 | + make the mounting location clear: |
| 61 | + |
| 62 | +  |
| 63 | + |
| 64 | + > Screw the base into the case only after the previous steps are done. Once |
| 65 | + > the base is fixed in the case there is not enough room for a screwdriver, |
| 66 | + > which makes joining the printed parts (step 1) very hard. |
| 67 | +
|
| 68 | +## Connections |
| 69 | + |
| 70 | +The following sections describe how to enable all of the following features: |
| 71 | + |
| 72 | +- serial connection to the platform, |
| 73 | +- controlling power supply, |
| 74 | +- enabling basic power actions with the platform (power off/power on/reset), |
| 75 | +- external flashing with the RTE, |
| 76 | + |
| 77 | +### Serial connection |
| 78 | + |
| 79 | +- Fit both jumpers, the TX one and the RX one, on the RTE [UART output select |
| 80 | + header](../../transparent-validation/rte/v1.1.0/specification.md#uart-output-select-header) |
| 81 | + (`J16`) to `RS232 + COM`. That routes the serial output to the DB9 |
| 82 | + connector. |
| 83 | +- Connect the IDC to RS232 adapter to the COM1 header on the motherboard. |
| 84 | + |
| 85 | +  |
| 86 | + |
| 87 | +- Connect the RS232 null modem cable to the RTE DB9 connector and to the IDC to |
| 88 | + RS232 adapter. |
| 89 | + |
| 90 | +  |
| 91 | + |
| 92 | +### Power supply controlling |
| 93 | + |
| 94 | +Connect the PSU power cord to the NOUS A1T smart outlet. |
| 95 | + |
| 96 | +### Basic power operations enabling |
| 97 | + |
| 98 | +Connect the RTE to the platform 9-pin PANEL1 header as described in the table. |
| 99 | +PWRBTN# and RESET# enable the power and reset operations. PLED+ is wired to the |
| 100 | +RTE J1 header for the device power status readout. |
| 101 | + |
| 102 | +| RTE | ASRock TURIND8UD PANEL1 header | |
| 103 | +| :-------: | :----------------------------: | |
| 104 | +| J11 pin 9 | PWRBTN# | |
| 105 | +| J11 pin 8 | RESET# | |
| 106 | +| J1 pin 1 | PLED+ | |
| 107 | + |
| 108 | +Cables connected to the RTE: |
| 109 | + |
| 110 | + |
| 111 | + |
| 112 | +Cables connected to the PANEL1 header on the motherboard: |
| 113 | + |
| 114 | + |
| 115 | + |
| 116 | +### External flashing enabling |
| 117 | + |
| 118 | +External flashing uses the SPI extender HAT (RTE SPI mux) on the RTE. The HAT |
| 119 | +exposes two SPI headers, `SPI_1` and `SPI_2`, each labeled `VCC`/`CS`/`MISO` on |
| 120 | +one row and `GND`/`CLK`/`MOSI` on the other. Always wire by the silkscreen |
| 121 | +label, not the pin position: the current mux revision swaps the two rows |
| 122 | +relative to the original |
| 123 | +[RTE SPI header](../../transparent-validation/rte/v1.1.0/specification.md#spi-header). |
| 124 | +Use `SPI_1` for the host boot flash and `SPI_2` for the BMC flash. |
| 125 | + |
| 126 | +**When flashing through the SPI extender HAT, do not follow the manual GPIO |
| 127 | +steps from the recovery guide. The HAT requires additional GPIOs to be set, |
| 128 | +which differs from the default RTE setup, so use `benchctl` - it sets them |
| 129 | +automatically.** |
| 130 | + |
| 131 | +#### Host boot flash |
| 132 | + |
| 133 | +The host BIOS SPI flash is programmed through the on-board TPM header, which |
| 134 | +exposes the SPI bus. An SPI flash TPM adapter PCB set carry the bus between the |
| 135 | +motherboard and the RTE, one on the motherboard `TPM_BIOS_PH_1` header and one |
| 136 | +on the SPI extender HAT, joined by a ribbon cable. Do not wire the TPM header |
| 137 | +with individual jumper wires - that wiring does not work reliably at the SPI |
| 138 | +clock used for flashing. |
| 139 | + |
| 140 | +The adapters come in two variants, one with an IDC connector and one with an FPC |
| 141 | +connector: |
| 142 | + |
| 143 | + |
| 144 | + |
| 145 | +Pick one pair and use it on both ends. The rest of this guide uses the FPC cable: |
| 146 | + |
| 147 | + |
| 148 | + |
| 149 | +The cable should be around 30 cm - longer cables may not work. |
| 150 | + |
| 151 | +Install the motherboard-side adapter before mounting the board in the case - it |
| 152 | +can also be done with the board already in the case, but it is harder. Install |
| 153 | +the PCB with the `TO MOBO` silkscreen (on the reverse side) onto the TPM header, |
| 154 | +aligned with the bolt hole, and make sure all pins sit tightly: |
| 155 | + |
| 156 | + |
| 157 | + |
| 158 | +The TPM module goes back on the adapter's pass-through header, so the platform |
| 159 | +keeps its TPM while the flash stays reachable: |
| 160 | + |
| 161 | + |
| 162 | + |
| 163 | +The second adapter mounts on the `SPI_1` header of the SPI extender HAT: |
| 164 | + |
| 165 | + |
| 166 | + |
| 167 | +Route the cable from the motherboard down to the HAT: |
| 168 | + |
| 169 | + |
| 170 | + |
| 171 | +For the TPM header pinout, refer to the |
| 172 | +[board's recovery section (setup with RTE)](../../variants/asrock_turind8ud/recovery.md#external-flashing). |
| 173 | + |
| 174 | +#### BMC flash |
| 175 | + |
| 176 | +`BMC_PH1` is a 2x5 1.27mm pitch header. Use the 1.27mm IDC connector to |
| 177 | +individual 2.54mm female connector cables to wire the `SPI_2` header to |
| 178 | +it according to the table: |
| 179 | + |
| 180 | +| `SPI_2` | BMC_PH1 pin | |
| 181 | +| :-----: | :---------: | |
| 182 | +| CS | 1 (CS#) | |
| 183 | +| VCC | 2 (VCC) | |
| 184 | +| MISO | 3 (SO/MISO) | |
| 185 | +| CLK | 6 (SCLK) | |
| 186 | +| MOSI | 8 (SI/MOSI) | |
| 187 | +| GND | 9 (GND) | |
| 188 | + |
| 189 | + |
| 190 | + |
| 191 | +### Complete Setup |
| 192 | + |
| 193 | +After preparing the connections, three activities should also be performed to |
| 194 | +enable all of the test stand features: |
| 195 | + |
| 196 | +1. Connect the NOUS A1T smart outlet to the mains: |
| 197 | + |
| 198 | +  |
| 199 | + |
| 200 | +1. Connect the RTE to the Internet by using the Ethernet cable. |
| 201 | + |
| 202 | +1. Connect the RTE to the mains by using the microUSB 5 V/2 A power supply. |
| 203 | + |
| 204 | +Full setup: |
| 205 | + |
| 206 | + |
| 207 | + |
| 208 | +## Theory of operation |
| 209 | + |
| 210 | +The following sections describe how to use all of the enabled features: |
| 211 | + |
| 212 | +- serial connection to the platform, |
| 213 | +- controlling power supply, |
| 214 | +- enabling basic power actions with the platform (power off/power on/reset), |
| 215 | +- external flashing with the RTE, |
| 216 | +- device power status readout. |
| 217 | + |
| 218 | +### Serial connection usage |
| 219 | + |
| 220 | +The method of setting and using serial connection is described in the |
| 221 | +[Serial connection guide](../../transparent-validation/rte/v1.1.0/serial-port-connection-guide.md). |
| 222 | + |
| 223 | +You can also use [benchctl](https://github.com/zarhus/benchctl), since default |
| 224 | +methods connect only to COM1 console which during OpenBMC development will |
| 225 | +likely output only BMC logs. To see host serial you have to use method, which |
| 226 | +`benchctl` assumes is via Serial-Over-LAN. |
| 227 | + |
| 228 | +- To connect to COM1 serial: |
| 229 | + |
| 230 | + ```sh |
| 231 | + benchctl --host <rte_ip_address> console |
| 232 | + ``` |
| 233 | + |
| 234 | +- To connect to Serial-Over-LAN console: |
| 235 | + |
| 236 | + ```sh |
| 237 | + benchctl --host <rte_ip_address> console --sol <bmc_ip_address> |
| 238 | + ``` |
| 239 | + |
| 240 | + This connects to the SoL with `ipmitool` via RTE (so BMC has to be reachable |
| 241 | + from RTE). |
| 242 | + |
| 243 | +### Power supply controlling |
| 244 | + |
| 245 | +Power supply controlling (in this case: controlling the state of the NOUS A1T |
| 246 | +smart outlet) is performed with |
| 247 | +[benchctl](https://github.com/zarhus/benchctl), which switches the outlet over |
| 248 | +its Tasmota HTTP API. Pass the outlet address with `--tasmota-ip`: |
| 249 | + |
| 250 | +1. Turn on the power supply: |
| 251 | + |
| 252 | + ```bash |
| 253 | + benchctl --host <rte_ip_address> \ |
| 254 | + power ac --tasmota-ip <sonoff_ip_address> on |
| 255 | + ``` |
| 256 | + |
| 257 | +1. Turn off the power supply: |
| 258 | + |
| 259 | + ```bash |
| 260 | + benchctl --host <rte_ip_address> \ |
| 261 | + power ac --tasmota-ip <sonoff_ip_address> off |
| 262 | + ``` |
| 263 | + |
| 264 | +1. Read the power supply state: |
| 265 | + |
| 266 | + ```bash |
| 267 | + benchctl --host <rte_ip_address> \ |
| 268 | + power ac --tasmota-ip <sonoff_ip_address> status |
| 269 | + ``` |
| 270 | + |
| 271 | +You can also power-cycle the mains feed with the `cycle` subcommand, which |
| 272 | +removes mains power completely and reapplies it after a brief wait: |
| 273 | + |
| 274 | +```bash |
| 275 | +benchctl --host <rte_ip_address> \ |
| 276 | + power ac --tasmota-ip <sonoff_ip_address> cycle |
| 277 | +``` |
| 278 | + |
| 279 | +> When using the BenchRack platform with an already prepared smart outlet |
| 280 | +> (connected to the RTE AP network), skip `--tasmota-ip` - the outlet is |
| 281 | +> reachable at `benchctl`'s default address: |
| 282 | +> |
| 283 | +> ```bash |
| 284 | +> benchctl --host <rte_ip_address> power ac on |
| 285 | +> ``` |
| 286 | +
|
| 287 | +### Basic power operations |
| 288 | +
|
| 289 | +Basic power operations should be performed with |
| 290 | +[benchctl](https://github.com/zarhus/benchctl). To perform basic power |
| 291 | +operations use the commands described below: |
| 292 | +
|
| 293 | +1. Turn on the platform: |
| 294 | +
|
| 295 | + ```bash |
| 296 | + benchctl --host <rte_ip_address> power on |
| 297 | + ``` |
| 298 | +
|
| 299 | +1. Turn off the platform: |
| 300 | +
|
| 301 | + ```bash |
| 302 | + benchctl --host <rte_ip_address> power off |
| 303 | + ``` |
| 304 | +
|
| 305 | +1. Reset the platform: |
| 306 | +
|
| 307 | + ```bash |
| 308 | + benchctl --host <rte_ip_address> power reset |
| 309 | + ``` |
| 310 | +
|
| 311 | +1. Read the power status: |
| 312 | +
|
| 313 | + The power status readout uses the PLED+ signal wired to the RTE J1 header and |
| 314 | + is reported by `benchctl`: |
| 315 | +
|
| 316 | + ```bash |
| 317 | + benchctl --host <rte_ip_address> power status |
| 318 | + ``` |
| 319 | +
|
| 320 | +> Note, that in order for the above commands to work properly, the platform |
| 321 | +> should be powered up: both the NOUS A1T smart outlet and the power supply must |
| 322 | +> be turned on. |
| 323 | +
|
| 324 | +### External flashing |
| 325 | +
|
| 326 | +The external flashing is performed with |
| 327 | +[benchctl](https://github.com/zarhus/benchctl), which can flash both the host |
| 328 | +BIOS flash and the BMC flash: |
| 329 | +
|
| 330 | +1. Flash the host firmware: |
| 331 | +
|
| 332 | + ```bash |
| 333 | + benchctl --host <rte_ip_address> flash write host <firmware> |
| 334 | + ``` |
| 335 | +
|
| 336 | +1. Flash the BMC firmware: |
| 337 | +
|
| 338 | + ```bash |
| 339 | + benchctl --host <rte_ip_address> flash write bmc <firmware> |
| 340 | + ``` |
| 341 | +
|
| 342 | +For external flashing hardware connection please refer to the |
| 343 | +[board's recovery section (setup with RTE)](../../variants/asrock_turind8ud/recovery.md#external-flashing). |
| 344 | + |
| 345 | +The AMD board takes longer to boot due to memory training happening on the PSP |
| 346 | +side. Thus the first signs of life from open-source firmware may appear even |
| 347 | +after a couple of minutes (depends on amount of populated RAM). |
| 348 | + |
| 349 | +### Ethernet |
| 350 | + |
| 351 | +The board's IPMI Ethernet (2) as well as a host Ethernet port (4 or 5) should be |
| 352 | +connected to the network. |
| 353 | +
|
| 354 | + |
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