These are not necessarily covered by the tutorial, but they are also important to reason about...
Q1 - What is the purpose of LEF/LIB/QRC files? Q2 - What is an upsized cell? Why do we use upsized cells? What is the meaning of an X16 cell, for instance? Q3 - What is the size of single flip-flop? Which file would you check to learn this information? Q4 - Regarging the timed path shown in the image, how many picosends are from combinational logic and how many are from sequential logic? Q5 - How is Genus able to estimate the net area if there is no layout? Q6 - If I have an asynchronous reset, how should I define my input delay w.r.t. the clock? Q7 - What is an integrated clock cell (ICG)? Why can't I do clock gating with a simple AND gate? Q8 - Is static power a function of the frequency? Q9 - Does it make sense to have a low syn_gen effort and a high syn_opt effort? Q10 - Does it make sense to have a high syn_gen effort and a low syn_opt effort? Q11 - Is the layout of an INVX1 LVT cell different from that of an INVX1 HVT? Q12 - Is it possible that the number of flip-flops will increase after retiming? Q13 - What would have happened if instead of adding flip-flops to the outputs we would have added them to the inputs? Q14 - Is the power estimation we got so far representative? How does Genus know how to calculate dynamic power?