TopOrigin.sv

// Generated by CIRCT firtool-1.62.0
// VCS coverage exclude_file
module regfile_32x32(
  input  [4:0]  R0_addr,
  input         R0_en,
                R0_clk,
  output [31:0] R0_data,
  input  [4:0]  R1_addr,
  input         R1_en,
                R1_clk,
  output [31:0] R1_data,
  input  [4:0]  W0_addr,
  input         W0_en,
                W0_clk,
  input  [31:0] W0_data
);

  reg [31:0] Memory[0:31];
  always @(posedge W0_clk) begin
    if (W0_en & 1'h1)
      Memory[W0_addr] <= W0_data;
  end // always @(posedge)
  assign R0_data = R0_en ? Memory[R0_addr] : 32'bx;
  assign R1_data = R1_en ? Memory[R1_addr] : 32'bx;
endmodule

module Core(
  input         clock,
                reset,
  output [31:0] io_imem_addr,
  input  [31:0] io_imem_inst,
  output [31:0] io_dmem_addr,
  input  [31:0] io_dmem_rdata,
  output        io_dmem_wen,
  output [31:0] io_dmem_wdata,
  output        io_exit
);

  wire        exe_jmp_flg;
  wire        exe_br_flg;
  wire [31:0] _regfile_ext_R0_data;
  wire [31:0] _regfile_ext_R1_data;
  reg  [31:0] id_reg_pc;
  reg  [31:0] id_reg_inst;
  reg  [31:0] exe_reg_pc;
  reg  [4:0]  exe_reg_wb_addr;
  reg  [31:0] exe_reg_op1_data;
  reg  [31:0] exe_reg_op2_data;
  reg  [31:0] exe_reg_rt_data;
  reg  [4:0]  exe_reg_exe_fun;
  reg  [1:0]  exe_reg_mem_wen;
  reg  [1:0]  exe_reg_rf_wen;
  reg  [2:0]  exe_reg_wb_sel;
  reg  [31:0] exe_reg_imm_i_sext;
  reg  [31:0] mem_reg_pc;
  reg  [4:0]  mem_reg_wb_addr;
  reg  [31:0] mem_reg_rt_data;
  reg  [1:0]  mem_reg_mem_wen;
  reg  [1:0]  mem_reg_rf_wen;
  reg  [2:0]  mem_reg_wb_sel;
  reg  [31:0] mem_reg_alu_out;
  reg  [4:0]  wb_reg_wb_addr;
  reg  [1:0]  wb_reg_rf_wen;
  reg  [31:0] wb_reg_wb_data;
  reg  [31:0] if_reg_pc;
  wire        _id_inst_T = exe_br_flg | exe_jmp_flg;
  wire        _id_rt_data_T_2 = exe_reg_rf_wen == 2'h1;
  wire        stall_flg =
    _id_rt_data_T_2 & (|(id_reg_inst[25:21])) & id_reg_inst[25:21] == exe_reg_wb_addr
    | _id_rt_data_T_2 & (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
  wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h20000000 : id_reg_inst;
  wire        _id_rt_data_T_8 = wb_reg_rf_wen == 2'h1;
  wire        _exe_alu_out_T = exe_reg_exe_fun == 5'h1;
  wire [31:0] _exe_alu_out_T_1 = exe_reg_op1_data + exe_reg_op2_data;
  wire        _exe_alu_out_T_3 = exe_reg_exe_fun == 5'h2;
  wire [31:0] _exe_alu_out_T_4 = exe_reg_op1_data - exe_reg_op2_data;
  wire        _exe_alu_out_T_6 = exe_reg_exe_fun == 5'h3;
  wire [31:0] _exe_alu_out_T_7 = exe_reg_op1_data & exe_reg_op2_data;
  wire        _exe_alu_out_T_8 = exe_reg_exe_fun == 5'h4;
  wire [31:0] _exe_alu_out_T_9 = exe_reg_op1_data | exe_reg_op2_data;
  wire        _exe_alu_out_T_10 = exe_reg_exe_fun == 5'h5;
  wire [31:0] _exe_alu_out_T_11 = exe_reg_op1_data ^ exe_reg_op2_data;
  wire        _exe_alu_out_T_12 = exe_reg_exe_fun == 5'h6;
  wire [62:0] _exe_alu_out_T_14 = {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
  wire        _exe_alu_out_T_16 = exe_reg_exe_fun == 5'h7;
  wire [31:0] _GEN = {27'h0, exe_reg_op2_data[4:0]};
  wire [31:0] _exe_alu_out_T_18 = exe_reg_op1_data >> _GEN;
  wire        _exe_alu_out_T_19 = exe_reg_exe_fun == 5'h8;
  wire [31:0] _exe_alu_out_T_22 = $signed($signed(exe_reg_op1_data) >>> _GEN);
  wire        _exe_alu_out_T_24 = exe_reg_exe_fun == 5'h9;
  wire        _exe_alu_out_T_28 = exe_reg_exe_fun == 5'hD;
  wire [31:0] _exe_alu_out_T_29 = _exe_alu_out_T_28 ? exe_reg_op1_data : 32'h0;
  wire [31:0] _GEN_0 = {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)};
  wire [31:0] exe_alu_out =
    _exe_alu_out_T
      ? _exe_alu_out_T_1
      : _exe_alu_out_T_3
          ? _exe_alu_out_T_4
          : _exe_alu_out_T_6
              ? _exe_alu_out_T_7
              : _exe_alu_out_T_8
                  ? _exe_alu_out_T_9
                  : _exe_alu_out_T_10
                      ? _exe_alu_out_T_11
                      : _exe_alu_out_T_12
                          ? _exe_alu_out_T_14[31:0]
                          : _exe_alu_out_T_16
                              ? _exe_alu_out_T_18
                              : _exe_alu_out_T_19
                                  ? _exe_alu_out_T_22
                                  : _exe_alu_out_T_24 ? _GEN_0 : _exe_alu_out_T_29;
  assign exe_br_flg =
    exe_reg_exe_fun == 5'hB
      ? exe_reg_op1_data == exe_reg_op2_data
      : exe_reg_exe_fun == 5'hC & exe_reg_op1_data != exe_reg_op2_data;
  assign exe_jmp_flg = exe_reg_wb_sel == 3'h3;
  wire [31:0] mem_wb_data =
    mem_reg_wb_sel == 3'h2
      ? io_dmem_rdata
      : mem_reg_wb_sel == 3'h3 ? mem_reg_pc + 32'h4 : mem_reg_alu_out;
  always @(posedge clock) begin
    if (reset) begin
      id_reg_pc <= 32'h0;
      id_reg_inst <= 32'h0;
      exe_reg_pc <= 32'h0;
      exe_reg_wb_addr <= 5'h0;
      exe_reg_op1_data <= 32'h0;
      exe_reg_op2_data <= 32'h0;
      exe_reg_rt_data <= 32'h0;
      exe_reg_exe_fun <= 5'h0;
      exe_reg_mem_wen <= 2'h0;
      exe_reg_rf_wen <= 2'h0;
      exe_reg_wb_sel <= 3'h0;
      exe_reg_imm_i_sext <= 32'h0;
      mem_reg_pc <= 32'h0;
      mem_reg_wb_addr <= 5'h0;
      mem_reg_rt_data <= 32'h0;
      mem_reg_mem_wen <= 2'h0;
      mem_reg_rf_wen <= 2'h0;
      mem_reg_wb_sel <= 3'h0;
      mem_reg_alu_out <= 32'h0;
      wb_reg_wb_addr <= 5'h0;
      wb_reg_rf_wen <= 2'h0;
      wb_reg_wb_data <= 32'h0;
      if_reg_pc <= 32'h0;
    end
    else begin
      automatic logic        _id_rt_data_T_5;
      automatic logic        _id_rt_data_T;
      automatic logic        _id_rt_data_T_3;
      automatic logic        _id_rt_data_T_6;
      automatic logic        _id_rt_data_T_9;
      automatic logic [31:0] id_imm_i_sext;
      automatic logic        _csignals_T_1 = id_inst[31:26] == 6'h23;
      automatic logic        _csignals_T_3;
      automatic logic [11:0] _GEN_1 = {id_inst[31:26], id_inst[5:0]};
      automatic logic        _csignals_T_5 = _GEN_1 == 12'h20;
      automatic logic        _csignals_T_7 = id_inst[31:26] == 6'h8;
      automatic logic        _csignals_T_9;
      automatic logic        _csignals_T_11;
      automatic logic        _csignals_T_13;
      automatic logic        _csignals_T_15;
      automatic logic        _csignals_T_17;
      automatic logic        _csignals_T_19;
      automatic logic        _csignals_T_21;
      automatic logic        _csignals_T_23;
      automatic logic        _csignals_T_25;
      automatic logic [16:0] _GEN_2 = {id_inst[31:21], id_inst[5:0]};
      automatic logic        _csignals_T_27;
      automatic logic        _csignals_T_29;
      automatic logic        _csignals_T_31;
      automatic logic        _csignals_T_33;
      automatic logic        _csignals_T_35;
      automatic logic        _GEN_3;
      automatic logic        _GEN_4;
      automatic logic [1:0]  csignals_1;
      automatic logic [2:0]  csignals_2;
      automatic logic        _GEN_5;
      automatic logic        _GEN_6;
      _id_rt_data_T_5 = mem_reg_rf_wen == 2'h1;
      _id_rt_data_T = id_inst[20:16] == 5'h0;
      _id_rt_data_T_3 = id_inst[20:16] == exe_reg_wb_addr & _id_rt_data_T_2;
      _id_rt_data_T_6 = id_inst[20:16] == mem_reg_wb_addr & _id_rt_data_T_5;
      _id_rt_data_T_9 = id_inst[20:16] == wb_reg_wb_addr & _id_rt_data_T_8;
      id_imm_i_sext = {{16{id_inst[15]}}, id_inst[15:0]};
      _csignals_T_3 = id_inst[31:26] == 6'h2B;
      _csignals_T_9 = _GEN_1 == 12'h22;
      _csignals_T_11 = _GEN_1 == 12'h24;
      _csignals_T_13 = _GEN_1 == 12'h25;
      _csignals_T_15 = _GEN_1 == 12'h26;
      _csignals_T_17 = id_inst[31:26] == 6'hC;
      _csignals_T_19 = id_inst[31:26] == 6'hD;
      _csignals_T_21 = _GEN_1 == 12'h2A;
      _csignals_T_23 = id_inst[31:26] == 6'h4;
      _csignals_T_25 = id_inst[31:26] == 6'h5;
      _csignals_T_27 = _GEN_2 == 17'h0;
      _csignals_T_29 = _GEN_2 == 17'h2;
      _csignals_T_31 = _GEN_2 == 17'h3;
      _csignals_T_33 = id_inst[31:26] == 6'h3;
      _csignals_T_35 = _GEN_1 == 12'h8;
      _GEN_3 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31;
      _GEN_4 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_3;
      csignals_1 =
        _csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7 | _csignals_T_9
        | _csignals_T_11 | _csignals_T_13 | _csignals_T_15 | _csignals_T_17
        | _csignals_T_19 | _GEN_4 | ~_csignals_T_33
          ? 2'h1
          : 2'h2;
      csignals_2 =
        _csignals_T_1 | _csignals_T_3
          ? 3'h2
          : _csignals_T_5
              ? 3'h1
              : _csignals_T_7
                  ? 3'h2
                  : _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
                      ? 3'h1
                      : _csignals_T_17 | _csignals_T_19
                          ? 3'h2
                          : _GEN_4
                              ? 3'h1
                              : _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35};
      _GEN_5 = _csignals_T_23 | _csignals_T_25;
      _GEN_6 =
        _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
        | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21;
      if (~stall_flg)
        id_reg_pc <= if_reg_pc;
      if (_id_inst_T)
        id_reg_inst <= 32'h20000000;
      else if (~stall_flg)
        id_reg_inst <= io_imem_inst;
      exe_reg_pc <= id_reg_pc;
      if ((_csignals_T_1
             ? 3'h2
             : _csignals_T_3
                 ? 3'h0
                 : _GEN_6
                     ? 3'h1
                     : _GEN_5
                         ? 3'h0
                         : _GEN_3 ? 3'h1 : _csignals_T_33 ? 3'h3 : 3'h0) == 3'h1
          & id_inst[31:26] == 6'h0)
        exe_reg_wb_addr <= id_inst[15:11];
      else if (id_inst[31:26] == 6'h3)
        exe_reg_wb_addr <= 5'h1F;
      else
        exe_reg_wb_addr <= id_inst[20:16];
      if (csignals_1 == 2'h1) begin
        if (id_inst[25:21] == 5'h0)
          exe_reg_op1_data <= 32'h0;
        else if (id_inst[25:21] == exe_reg_wb_addr & _id_rt_data_T_2) begin
          if (_exe_alu_out_T)
            exe_reg_op1_data <= _exe_alu_out_T_1;
          else if (_exe_alu_out_T_3)
            exe_reg_op1_data <= _exe_alu_out_T_4;
          else if (_exe_alu_out_T_6)
            exe_reg_op1_data <= _exe_alu_out_T_7;
          else if (_exe_alu_out_T_8)
            exe_reg_op1_data <= _exe_alu_out_T_9;
          else if (_exe_alu_out_T_10)
            exe_reg_op1_data <= _exe_alu_out_T_11;
          else if (_exe_alu_out_T_12)
            exe_reg_op1_data <= _exe_alu_out_T_14[31:0];
          else if (_exe_alu_out_T_16)
            exe_reg_op1_data <= _exe_alu_out_T_18;
          else if (_exe_alu_out_T_19)
            exe_reg_op1_data <= _exe_alu_out_T_22;
          else if (_exe_alu_out_T_24)
            exe_reg_op1_data <= _GEN_0;
          else if (~_exe_alu_out_T_28)
            exe_reg_op1_data <= 32'h0;
        end
        else if (id_inst[25:21] == mem_reg_wb_addr & _id_rt_data_T_5)
          exe_reg_op1_data <= mem_wb_data;
        else if (id_inst[25:21] == wb_reg_wb_addr & _id_rt_data_T_8)
          exe_reg_op1_data <= wb_reg_wb_data;
        else
          exe_reg_op1_data <= _regfile_ext_R1_data;
      end
      else if (csignals_1 == 2'h2)
        exe_reg_op1_data <= id_reg_pc;
      else
        exe_reg_op1_data <= 32'h0;
      if (csignals_2 == 3'h1) begin
        if (_id_rt_data_T)
          exe_reg_op2_data <= 32'h0;
        else if (_id_rt_data_T_3) begin
          if (_exe_alu_out_T)
            exe_reg_op2_data <= _exe_alu_out_T_1;
          else if (_exe_alu_out_T_3)
            exe_reg_op2_data <= _exe_alu_out_T_4;
          else if (_exe_alu_out_T_6)
            exe_reg_op2_data <= _exe_alu_out_T_7;
          else if (_exe_alu_out_T_8)
            exe_reg_op2_data <= _exe_alu_out_T_9;
          else if (_exe_alu_out_T_10)
            exe_reg_op2_data <= _exe_alu_out_T_11;
          else if (_exe_alu_out_T_12)
            exe_reg_op2_data <= _exe_alu_out_T_14[31:0];
          else if (_exe_alu_out_T_16)
            exe_reg_op2_data <= _exe_alu_out_T_18;
          else if (_exe_alu_out_T_19)
            exe_reg_op2_data <= _exe_alu_out_T_22;
          else if (_exe_alu_out_T_24)
            exe_reg_op2_data <= _GEN_0;
          else
            exe_reg_op2_data <= _exe_alu_out_T_29;
        end
        else if (_id_rt_data_T_6)
          exe_reg_op2_data <= mem_wb_data;
        else if (_id_rt_data_T_9)
          exe_reg_op2_data <= wb_reg_wb_data;
        else
          exe_reg_op2_data <= _regfile_ext_R0_data;
      end
      else if (csignals_2 == 3'h2)
        exe_reg_op2_data <= id_imm_i_sext;
      else if (csignals_2 == 3'h4)
        exe_reg_op2_data <= {4'h0, id_inst[25:0], 2'h0};
      else
        exe_reg_op2_data <= 32'h0;
      exe_reg_rt_data <=
        _id_rt_data_T
          ? 32'h0
          : _id_rt_data_T_3
              ? exe_alu_out
              : _id_rt_data_T_6
                  ? mem_wb_data
                  : _id_rt_data_T_9 ? wb_reg_wb_data : _regfile_ext_R0_data;
      if (_csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7)
        exe_reg_exe_fun <= 5'h1;
      else if (_csignals_T_9)
        exe_reg_exe_fun <= 5'h2;
      else if (_csignals_T_11)
        exe_reg_exe_fun <= 5'h3;
      else if (_csignals_T_13)
        exe_reg_exe_fun <= 5'h4;
      else if (_csignals_T_15)
        exe_reg_exe_fun <= 5'h5;
      else if (_csignals_T_17)
        exe_reg_exe_fun <= 5'h3;
      else if (_csignals_T_19)
        exe_reg_exe_fun <= 5'h4;
      else if (_csignals_T_21)
        exe_reg_exe_fun <= 5'h9;
      else if (_csignals_T_23)
        exe_reg_exe_fun <= 5'hB;
      else if (_csignals_T_25)
        exe_reg_exe_fun <= 5'hC;
      else if (_csignals_T_27)
        exe_reg_exe_fun <= 5'h6;
      else if (_csignals_T_29)
        exe_reg_exe_fun <= 5'h7;
      else if (_csignals_T_31)
        exe_reg_exe_fun <= 5'h8;
      else if (_csignals_T_33)
        exe_reg_exe_fun <= 5'h1;
      else if (_csignals_T_35)
        exe_reg_exe_fun <= 5'hD;
      else
        exe_reg_exe_fun <= 5'h0;
      exe_reg_mem_wen <= _csignals_T_1 ? 2'h0 : {1'h0, _csignals_T_3};
      if (_csignals_T_1) begin
        exe_reg_rf_wen <= 2'h1;
        exe_reg_wb_sel <= 3'h2;
      end
      else if (_csignals_T_3) begin
        exe_reg_rf_wen <= 2'h0;
        exe_reg_wb_sel <= 3'h0;
      end
      else if (_GEN_6) begin
        exe_reg_rf_wen <= 2'h1;
        exe_reg_wb_sel <= 3'h1;
      end
      else if (_GEN_5) begin
        exe_reg_rf_wen <= 2'h0;
        exe_reg_wb_sel <= 3'h0;
      end
      else begin
        exe_reg_rf_wen <=
          {1'h0, _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33};
        if (_GEN_3)
          exe_reg_wb_sel <= 3'h1;
        else if (_csignals_T_33)
          exe_reg_wb_sel <= 3'h3;
        else
          exe_reg_wb_sel <= 3'h0;
      end
      exe_reg_imm_i_sext <= id_imm_i_sext;
      mem_reg_pc <= exe_reg_pc;
      mem_reg_wb_addr <= exe_reg_wb_addr;
      mem_reg_rt_data <= exe_reg_rt_data;
      mem_reg_mem_wen <= exe_reg_mem_wen;
      mem_reg_rf_wen <= exe_reg_rf_wen;
      mem_reg_wb_sel <= exe_reg_wb_sel;
      mem_reg_alu_out <= exe_alu_out;
      wb_reg_wb_addr <= mem_reg_wb_addr;
      wb_reg_rf_wen <= mem_reg_rf_wen;
      wb_reg_wb_data <= mem_wb_data;
      if (exe_br_flg)
        if_reg_pc <= {exe_reg_imm_i_sext[29:0], 2'h0} + exe_reg_pc;
      else if (exe_jmp_flg)
        if_reg_pc <= exe_alu_out;
      else if (~stall_flg)
        if_reg_pc <= if_reg_pc + 32'h4;
    end
  end // always @(posedge)
  regfile_32x32 regfile_ext (
    .R0_addr (id_inst[20:16]),
    .R0_en   (1'h1),
    .R0_clk  (clock),
    .R0_data (_regfile_ext_R0_data),
    .R1_addr (id_inst[25:21]),
    .R1_en   (1'h1),
    .R1_clk  (clock),
    .R1_data (_regfile_ext_R1_data),
    .W0_addr (wb_reg_wb_addr),
    .W0_en   (_id_rt_data_T_8 & (|wb_reg_wb_addr)),
    .W0_clk  (clock),
    .W0_data (wb_reg_wb_data)
  );
  assign io_imem_addr = if_reg_pc;
  assign io_dmem_addr = mem_reg_alu_out;
  assign io_dmem_wen = mem_reg_mem_wen[0];
  assign io_dmem_wdata = mem_reg_rt_data;
  assign io_exit = id_reg_inst == 32'h114514;
endmodule

// VCS coverage exclude_file
module mem_64x32(
  input  [5:0]  R0_addr,
  input         R0_en,
                R0_clk,
  output [31:0] R0_data,
  input  [5:0]  R1_addr,
  input         R1_en,
                R1_clk,
  output [31:0] R1_data,
  input  [5:0]  W0_addr,
  input         W0_en,
                W0_clk,
  input  [31:0] W0_data
);

  reg [31:0] Memory[0:63];
  always @(posedge W0_clk) begin
    if (W0_en & 1'h1)
      Memory[W0_addr] <= W0_data;
  end // always @(posedge)
  `ifdef ENABLE_INITIAL_MEM_
    initial
      $readmemh("src/hex/mem.dat", Memory);
  `endif // ENABLE_INITIAL_MEM_
  assign R0_data = R0_en ? Memory[R0_addr] : 32'bx;
  assign R1_data = R1_en ? Memory[R1_addr] : 32'bx;
endmodule

module Memory(
  input         clock,
  input  [31:0] io_imem_addr,
  output [31:0] io_imem_inst,
  input  [31:0] io_dmem_addr,
  output [31:0] io_dmem_rdata,
  input         io_dmem_wen,
  input  [31:0] io_dmem_wdata
);

  mem_64x32 mem_ext (
    .R0_addr (io_imem_addr[7:2]),
    .R0_en   (1'h1),
    .R0_clk  (clock),
    .R0_data (io_imem_inst),
    .R1_addr (io_dmem_addr[7:2]),
    .R1_en   (1'h1),
    .R1_clk  (clock),
    .R1_data (io_dmem_rdata),
    .W0_addr (io_dmem_addr[7:2]),
    .W0_en   (io_dmem_wen),
    .W0_clk  (clock),
    .W0_data (io_dmem_wdata)
  );
endmodule

module TopOrigin(
  input  clock,
         reset,
  output io_exit
);

  wire [31:0] _memory_io_imem_inst;
  wire [31:0] _memory_io_dmem_rdata;
  wire [31:0] _core_io_imem_addr;
  wire [31:0] _core_io_dmem_addr;
  wire        _core_io_dmem_wen;
  wire [31:0] _core_io_dmem_wdata;
  Core core (
    .clock         (clock),
    .reset         (reset),
    .io_imem_addr  (_core_io_imem_addr),
    .io_imem_inst  (_memory_io_imem_inst),
    .io_dmem_addr  (_core_io_dmem_addr),
    .io_dmem_rdata (_memory_io_dmem_rdata),
    .io_dmem_wen   (_core_io_dmem_wen),
    .io_dmem_wdata (_core_io_dmem_wdata),
    .io_exit       (io_exit)
  );
  Memory memory (
    .clock         (clock),
    .io_imem_addr  (_core_io_imem_addr),
    .io_imem_inst  (_memory_io_imem_inst),
    .io_dmem_addr  (_core_io_dmem_addr),
    .io_dmem_rdata (_memory_io_dmem_rdata),
    .io_dmem_wen   (_core_io_dmem_wen),
    .io_dmem_wdata (_core_io_dmem_wdata)
  );
endmodule