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jakubcabaljakubcabal
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Merge branch 'cabal_dma_eps_mod' into 'devel'
Optimization to improve PCIe Gen5 x16 configuration performance See merge request ndk/ndk-fpga!256
2 parents 397bc0a + 4e1f752 commit 773b687

12 files changed

Lines changed: 253 additions & 86 deletions

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‎apps/minimal/build/agi-fh400g/jenkins/400g1_rev0_pcie_1xgen5x16.jenkinsfile‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
library 'liberouter'
2+
3+
stagesFirmware(
4+
dir: 'apps/minimal/build/agi-fh400g',
5+
target: '400g1',
6+
tool: 'quartus',
7+
quartus: '22.4.0.94',
8+
project: 'agi-fh400g-rev0-minimal-pcie1xgen5x16-400g1',
9+
params: 'BOARD_REV=0 PCIE_CONF=1xgen5x16',
10+
pollscm: 'H H(0-11) * * 6',
11+
rpms: false,
12+
rename: false,
13+
artifacts: 'agi-fh400g-rev0-minimal-pcie1xgen5x16-400g1',
14+
lastBuilds: 2,
15+
)

‎apps/minimal/build/agi-fh400g/jenkins/400g1_rev1_pcie_1xgen5x16.jenkinsfile‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
library 'liberouter'
2+
3+
stagesFirmware(
4+
dir: 'apps/minimal/build/agi-fh400g',
5+
target: '400g1',
6+
tool: 'quartus',
7+
project: 'agi-fh400g-rev1-minimal-pcie1xgen5x16-400g1',
8+
params: 'BOARD_REV=1 PCIE_CONF=1xgen5x16',
9+
pollscm: 'H H(0-11) * * 6',
10+
rpms: false,
11+
rename: false,
12+
artifacts: 'agi-fh400g-rev1-minimal-pcie1xgen5x16-400g1',
13+
lastBuilds: 2,
14+
)

‎cards/reflexces/agi-fh400g/config/card_const.tcl‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -40,19 +40,17 @@ if { $BOARD_REV != 0 && $BOARD_REV != 1 && $BOARD_REV != 2} {
4040
}
4141

4242
if {!(($PCIE_ENDPOINTS == 1 && $PCIE_GEN == 4 && $PCIE_ENDPOINT_MODE == 0) ||
43+
($PCIE_ENDPOINTS == 1 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 0) ||
4344
($PCIE_ENDPOINTS == 4 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 1) ||
4445
($PCIE_ENDPOINTS == 2 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 1) )} {
4546
error "Incompatible PCIe configuration: PCIE_ENDPOINTS = $PCIE_ENDPOINTS, PCIE_GEN = $PCIE_GEN, PCIE_ENDPOINT_MODE = $PCIE_ENDPOINT_MODE!
4647
Allowed PCIe configurations:
4748
- 2xGen5x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=4, PCIE_ENDPOINT_MODE=1 (for DMA Medusa only)
4849
- 1xGen5x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1 (for DMA Medusa only)
50+
- 1xGen5x16 -- PCIE_GEN=5, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 (for DMA Medusa only, experimental!)
4951
- 1xGen4x16 -- PCIE_GEN=4, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0 (for DMA Calypte only)"
5052
}
5153

52-
# Enable/add PCIe Gen5 x16 for experiments only!
53-
#($PCIE_ENDPOINTS == 1 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 0) ||
54-
#- 1xGen5x16 -- PCIE_GEN=5, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0"
55-
5654
# ------------------------------------------------------------------------------
5755
# Other parameters:
5856
# ------------------------------------------------------------------------------

‎comp/mfb_tools/flow/merger/Modules.tcl‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@ set MFB_PIPE_BASE "$OFM_PATH/comp/mfb_tools/flow/pipe"
1111
set PIPE_REG_BASE "$OFM_PATH/comp/base/misc/pipe"
1212
set SHAKEDOWN_BASE "$OFM_PATH/comp/mvb_tools/flow/shakedown"
1313
set MVB_MERGE_ST_BASE "$OFM_PATH/comp/mvb_tools/flow/merge_streams"
14+
set MFB_FIFOX_BASE "$OFM_PATH/comp/mfb_tools/storage/fifox"
1415

1516
set PKG_BASE "$OFM_PATH/comp/base/pkg"
1617

@@ -26,6 +27,7 @@ lappend COMPONENTS [ list "MFB_PIPE" $MFB_PIPE_BASE "FULL" ]
2627
lappend COMPONENTS [ list "PIPE_REG" $PIPE_REG_BASE "FULL" ]
2728
lappend COMPONENTS [ list "SHAKEDOWN" $SHAKEDOWN_BASE "FULL" ]
2829
lappend COMPONENTS [ list "MVB_MERGE_ST" $MVB_MERGE_ST_BASE "FULL" ]
30+
lappend COMPONENTS [ list "MFB_FIFOX" $MFB_FIFOX_BASE "FULL" ]
2931

3032
# Source files for implemented component
3133
set MOD "$MOD $ENTITY_BASE/mfb_merger_ent.vhd"

‎comp/mfb_tools/flow/merger/mfb_merger_ent.vhd‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -57,8 +57,10 @@ entity MFB_MERGER is
5757
RX0_PAYLOAD_ENABLED : boolean := true;
5858
RX1_PAYLOAD_ENABLED : boolean := true;
5959

60+
-- To enable optional MFB FIFOs at input
61+
IN_MFB_FIFO_EN : boolean := false;
62+
6063
-- Size of input MVB and MFB FIFOs (in words)
61-
-- Only used in architecture FULL.
6264
-- Minimum value is 2!
6365
INPUT_FIFO_SIZE : integer := 8;
6466

‎comp/mfb_tools/flow/merger/mfb_merger_full.vhd‎

Lines changed: 77 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,16 @@ architecture FULL of MFB_MERGER is
6868
signal rx_mvb_hdr_p_arr : slv_array_2d_t(2-1 downto 0)(MVB_ITEMS-1 downto 0)(1+HDR_WIDTH-1 downto 0);
6969
signal rx_mvb_hdr_p : slv_array_t(2-1 downto 0)(MVB_ITEMS*(1+HDR_WIDTH)-1 downto 0);
7070

71+
-- RX MFB FIFO signals
72+
signal rx_fifo_mfb_data : slv_array_t(2-1 downto 0)(MFB_REGIONS*MFB_DATA_WIDTH-1 downto 0);
73+
signal rx_fifo_mfb_meta : slv_array_t(2-1 downto 0)(MFB_REGIONS*MFB_META_WIDTH-1 downto 0);
74+
signal rx_fifo_mfb_sof : slv_array_t(2-1 downto 0)(MFB_REGIONS-1 downto 0);
75+
signal rx_fifo_mfb_eof : slv_array_t(2-1 downto 0)(MFB_REGIONS-1 downto 0);
76+
signal rx_fifo_mfb_sof_pos : slv_array_t(2-1 downto 0)(MFB_REGIONS*SOF_POS_WIDTH-1 downto 0);
77+
signal rx_fifo_mfb_eof_pos : slv_array_t(2-1 downto 0)(MFB_REGIONS*EOF_POS_WIDTH-1 downto 0);
78+
signal rx_fifo_mfb_src_rdy : std_logic_vector(2-1 downto 0);
79+
signal rx_fifo_mfb_dst_rdy : std_logic_vector(2-1 downto 0);
80+
7181
-----------------------------------------------
7282

7383
-- RX MVB hdr from input PIPEs with payload added
@@ -295,6 +305,57 @@ begin
295305

296306
-- -------------------------------------------------------------------------
297307

308+
-- -------------------------------------------------------------------------
309+
-- Optional Input FIFOs
310+
-- -------------------------------------------------------------------------
311+
312+
in_mfb_fifo_g : for ii in 0 to 2-1 generate
313+
in_mfb_fifo_g2 : if (IN_MFB_FIFO_EN = True) generate
314+
mfb_fifo_i : entity work.MFB_FIFOX
315+
generic map (
316+
REGIONS => MFB_REGIONS,
317+
REGION_SIZE => MFB_REG_SIZE,
318+
BLOCK_SIZE => MFB_BLOCK_SIZE,
319+
ITEM_WIDTH => MFB_ITEM_WIDTH,
320+
META_WIDTH => MFB_META_WIDTH,
321+
FIFO_DEPTH => INPUT_FIFO_SIZE,
322+
RAM_TYPE => "AUTO",
323+
DEVICE => DEVICE
324+
)
325+
port map (
326+
CLK => CLK,
327+
RST => RESET,
328+
329+
RX_DATA => rx_mfb_data(ii),
330+
RX_META => rx_mfb_meta(ii),
331+
RX_SOF_POS => rx_mfb_sof_pos(ii),
332+
RX_EOF_POS => rx_mfb_eof_pos(ii),
333+
RX_SOF => rx_mfb_sof(ii),
334+
RX_EOF => rx_mfb_eof(ii),
335+
RX_SRC_RDY => rx_mfb_src_rdy(ii),
336+
RX_DST_RDY => rx_mfb_dst_rdy(ii),
337+
338+
TX_DATA => rx_fifo_mfb_data(ii),
339+
TX_META => rx_fifo_mfb_meta(ii),
340+
TX_SOF_POS => rx_fifo_mfb_sof_pos(ii),
341+
TX_EOF_POS => rx_fifo_mfb_eof_pos(ii),
342+
TX_SOF => rx_fifo_mfb_sof(ii),
343+
TX_EOF => rx_fifo_mfb_eof(ii),
344+
TX_SRC_RDY => rx_fifo_mfb_src_rdy(ii),
345+
TX_DST_RDY => rx_fifo_mfb_dst_rdy(ii)
346+
);
347+
else generate
348+
rx_fifo_mfb_data(ii) <= rx_mfb_data(ii);
349+
rx_fifo_mfb_meta(ii) <= rx_mfb_meta(ii);
350+
rx_fifo_mfb_sof_pos(ii) <= rx_mfb_sof_pos(ii);
351+
rx_fifo_mfb_eof_pos(ii) <= rx_mfb_eof_pos(ii);
352+
rx_fifo_mfb_sof(ii) <= rx_mfb_sof(ii);
353+
rx_fifo_mfb_eof(ii) <= rx_mfb_eof(ii);
354+
rx_fifo_mfb_src_rdy(ii) <= rx_mfb_src_rdy(ii);
355+
rx_mfb_dst_rdy(ii) <= rx_fifo_mfb_dst_rdy(ii);
356+
end generate;
357+
end generate;
358+
298359
no_in_pipe_gen : if (IN_PIPE_EN = false) generate
299360

300361
-- -------------------------------------------------------------------------
@@ -308,14 +369,14 @@ begin
308369
rx_in_pipe_mvb_src_rdy(i) <= rx_mvb_src_rdy(i);
309370
rx_mvb_dst_rdy (i) <= rx_in_pipe_mvb_dst_rdy(i);
310371

311-
rx_in_pipe_mfb_data (i) <= rx_mfb_data (i);
312-
rx_in_pipe_mfb_meta (i) <= rx_mfb_meta (i);
313-
rx_in_pipe_mfb_sof (i) <= rx_mfb_sof (i);
314-
rx_in_pipe_mfb_eof (i) <= rx_mfb_eof (i);
315-
rx_in_pipe_mfb_sof_pos(i) <= rx_mfb_sof_pos(i);
316-
rx_in_pipe_mfb_eof_pos(i) <= rx_mfb_eof_pos(i);
317-
rx_in_pipe_mfb_src_rdy(i) <= rx_mfb_src_rdy(i);
318-
rx_mfb_dst_rdy (i) <= rx_in_pipe_mfb_dst_rdy(i);
372+
rx_in_pipe_mfb_data (i) <= rx_fifo_mfb_data (i);
373+
rx_in_pipe_mfb_meta (i) <= rx_fifo_mfb_meta (i);
374+
rx_in_pipe_mfb_sof (i) <= rx_fifo_mfb_sof (i);
375+
rx_in_pipe_mfb_eof (i) <= rx_fifo_mfb_eof (i);
376+
rx_in_pipe_mfb_sof_pos(i) <= rx_fifo_mfb_sof_pos(i);
377+
rx_in_pipe_mfb_eof_pos(i) <= rx_fifo_mfb_eof_pos(i);
378+
rx_in_pipe_mfb_src_rdy(i) <= rx_fifo_mfb_src_rdy(i);
379+
rx_fifo_mfb_dst_rdy (i) <= rx_in_pipe_mfb_dst_rdy(i);
319380
end generate;
320381

321382
-- -------------------------------------------------------------------------
@@ -403,14 +464,14 @@ begin
403464
CLK => CLK,
404465
RESET => RESET,
405466

406-
RX_DATA => rx_mfb_data (i),
407-
RX_META => rx_mfb_meta (i),
408-
RX_SOF_POS => rx_mfb_sof_pos(i),
409-
RX_EOF_POS => rx_mfb_eof_pos(i),
410-
RX_SOF => rx_mfb_sof (i),
411-
RX_EOF => rx_mfb_eof (i),
412-
RX_SRC_RDY => rx_mfb_src_rdy(i),
413-
RX_DST_RDY => rx_mfb_dst_rdy(i),
467+
RX_DATA => rx_fifo_mfb_data (i),
468+
RX_META => rx_fifo_mfb_meta (i),
469+
RX_SOF_POS => rx_fifo_mfb_sof_pos(i),
470+
RX_EOF_POS => rx_fifo_mfb_eof_pos(i),
471+
RX_SOF => rx_fifo_mfb_sof (i),
472+
RX_EOF => rx_fifo_mfb_eof (i),
473+
RX_SRC_RDY => rx_fifo_mfb_src_rdy(i),
474+
RX_DST_RDY => rx_fifo_mfb_dst_rdy(i),
414475

415476
TX_DATA => rx_in_pipe_mfb_data (i),
416477
TX_META => rx_in_pipe_mfb_meta (i),

‎comp/mfb_tools/flow/merger/mfb_merger_gen.vhd‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,9 @@ entity MFB_MERGER_GEN is
6363
-- the next active MVB/MFB stream occurs.
6464
SW_TIMEOUT_WIDTH : natural := 4;
6565

66+
-- To enable optional MFB FIFOs at middle stages
67+
MID_MFB_FIFOS_EN : boolean := False;
68+
6669
-- Input PIPEs enable for all 2:1 Mergers
6770
-- Input registers is created when this is set to false.
6871
IN_PIPE_EN : boolean := false;
@@ -206,6 +209,7 @@ begin
206209
HDR_WIDTH => MVB_ITEM_WIDTH,
207210
RX0_PAYLOAD_ENABLED => get_payload_en(s,2*i ),
208211
RX1_PAYLOAD_ENABLED => get_payload_en(s,2*i+1),
212+
IN_MFB_FIFO_EN => (s /= 0 and MID_MFB_FIFOS_EN),
209213
INPUT_FIFO_SIZE => INPUT_FIFO_SIZE,
210214
SW_TIMEOUT_WIDTH => SW_TIMEOUT_WIDTH,
211215
IN_PIPE_EN => IN_PIPE_EN,

‎comp/mfb_tools/flow/splitter/Modules.tcl‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77
set FIFOXM_BASE "$OFM_PATH/comp/base/fifo/fifox_multi"
88
set FIFOX_BASE "$OFM_PATH/comp/base/fifo/fifox"
99
set SPLITTER_BASE "$OFM_PATH/comp/mfb_tools/flow/splitter_simple"
10+
set MFB_FIFOX_BASE "$OFM_PATH/comp/mfb_tools/storage/fifox"
1011

1112
set PKG_BASE "$OFM_PATH/comp/base/pkg"
1213

@@ -19,6 +20,7 @@ set COMPONENTS [ list \
1920
[ list "FIFOX_MULTI" $FIFOXM_BASE "FULL" ] \
2021
[ list "FIFOX" $FIFOX_BASE "FULL" ] \
2122
[ list "SPLITTER" $SPLITTER_BASE "FULL" ] \
23+
[ list "MFB_FIFOX" $MFB_FIFOX_BASE "FULL" ] \
2224
]
2325

2426
# entity and architecture

‎comp/mfb_tools/flow/splitter/mfb_splitter.vhd‎

Lines changed: 66 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -54,6 +54,12 @@ entity MFB_SPLITTER is
5454
-- The minimum value is 2
5555
MVB_OUTPUT_FIFO_SIZE : integer := 8;
5656

57+
-- To enable optional MFB FIFOs at input
58+
IN_MFB_FIFO_EN : boolean := false;
59+
60+
-- Size of MFB FIFOs (in words)
61+
MFB_FIFO_DEPTH : natural := 512;
62+
5763
-- Create output register PIPEs
5864
USE_OUTREG : boolean := true;
5965

@@ -149,6 +155,14 @@ architecture FULL of MFB_SPLITTER is
149155
-- Signals
150156
---------------------------------------------------------------------------
151157

158+
signal rx_fifo_mfb_data : std_logic_vector(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0);
159+
signal rx_fifo_mfb_sof : std_logic_vector(MFB_REGIONS-1 downto 0);
160+
signal rx_fifo_mfb_eof : std_logic_vector(MFB_REGIONS-1 downto 0);
161+
signal rx_fifo_mfb_sof_pos : std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE))-1 downto 0);
162+
signal rx_fifo_mfb_eof_pos : std_logic_vector(MFB_REGIONS*max(1,log2(MFB_REG_SIZE*MFB_BLOCK_SIZE))-1 downto 0);
163+
signal rx_fifo_mfb_src_rdy : std_logic;
164+
signal rx_fifo_mfb_dst_rdy : std_logic;
165+
152166
-- Valid for input MVB separated by its switch
153167
signal rx0_mvb_vld : std_logic_vector(MVB_ITEMS-1 downto 0);
154168
signal rx1_mvb_vld : std_logic_vector(MVB_ITEMS-1 downto 0);
@@ -224,7 +238,7 @@ begin
224238
);
225239

226240
switch_fifoxm_rd_gen : for i in 0 to MFB_REGIONS-1 generate
227-
switch_fifoxm_rd(i) <= '1' when can_send_whole = '1' and i < rx_mfb_sof_cnt(MFB_REGIONS) and RX_MFB_SRC_RDY = '1' and mfb_spl_rx_dst_rdy = '1' else '0';
241+
switch_fifoxm_rd(i) <= '1' when can_send_whole = '1' and i < rx_mfb_sof_cnt(MFB_REGIONS) and rx_fifo_mfb_src_rdy = '1' and mfb_spl_rx_dst_rdy = '1' else '0';
228242
end generate;
229243

230244
-- shift empty signal
@@ -236,15 +250,56 @@ begin
236250
-- MFB sending
237251
-- -------------------------------------------------------------------------
238252

239-
-- Distribute switch info according to current RX_MFB_SOF positions
240-
switch_dist_pr : process (switch_fifoxm_do,RX_MFB_SOF,rx_mfb_sof_cnt)
253+
in_mfb_fifo_g : if (IN_MFB_FIFO_EN = True) generate
254+
mfb_fifo_i : entity work.MFB_FIFOX
255+
generic map (
256+
REGIONS => MFB_REGIONS,
257+
REGION_SIZE => MFB_REG_SIZE,
258+
BLOCK_SIZE => MFB_BLOCK_SIZE,
259+
ITEM_WIDTH => MFB_ITEM_WIDTH,
260+
FIFO_DEPTH => MFB_FIFO_DEPTH,
261+
RAM_TYPE => "AUTO",
262+
DEVICE => DEVICE
263+
)
264+
port map (
265+
CLK => CLK,
266+
RST => RESET,
267+
268+
RX_DATA => RX_MFB_DATA,
269+
RX_SOF_POS => RX_MFB_SOF_POS,
270+
RX_EOF_POS => RX_MFB_EOF_POS,
271+
RX_SOF => RX_MFB_SOF,
272+
RX_EOF => RX_MFB_EOF,
273+
RX_SRC_RDY => RX_MFB_SRC_RDY,
274+
RX_DST_RDY => RX_MFB_DST_RDY,
275+
276+
TX_DATA => rx_fifo_mfb_data,
277+
TX_SOF_POS => rx_fifo_mfb_sof_pos,
278+
TX_EOF_POS => rx_fifo_mfb_eof_pos,
279+
TX_SOF => rx_fifo_mfb_sof,
280+
TX_EOF => rx_fifo_mfb_eof,
281+
TX_SRC_RDY => rx_fifo_mfb_src_rdy,
282+
TX_DST_RDY => rx_fifo_mfb_dst_rdy
283+
);
284+
else generate
285+
rx_fifo_mfb_data <= RX_MFB_DATA;
286+
rx_fifo_mfb_sof_pos <= RX_MFB_SOF_POS;
287+
rx_fifo_mfb_eof_pos <= RX_MFB_EOF_POS;
288+
rx_fifo_mfb_sof <= RX_MFB_SOF;
289+
rx_fifo_mfb_eof <= RX_MFB_EOF;
290+
rx_fifo_mfb_src_rdy <= RX_MFB_SRC_RDY;
291+
RX_MFB_DST_RDY <= rx_fifo_mfb_dst_rdy;
292+
end generate;
293+
294+
-- Distribute switch info according to current rx_fifo_mfb_sof positions
295+
switch_dist_pr : process (switch_fifoxm_do,rx_fifo_mfb_sof,rx_mfb_sof_cnt)
241296
variable cnt : integer;
242297
begin
243298
-- count number of SOFs before each region
244299
for i in 0 to MFB_REGIONS+1-1 loop
245300
cnt := 0;
246301
for e in 0 to i-1 loop
247-
if (RX_MFB_SOF(e) = '1') then
302+
if (rx_fifo_mfb_sof(e) = '1') then
248303
cnt := cnt+1;
249304
end if;
250305
end loop;
@@ -261,9 +316,9 @@ begin
261316
-- RX MFB can be passed when there is at least as much switch info on switch fifoxm output as there is SOFs in the RX MFB
262317
can_send_whole <= '1' when switch_fifoxm_empty_sh(to_integer(rx_mfb_sof_cnt(MFB_REGIONS))) = '0' else '0';
263318

264-
mfb_spl_rx_src_rdy <= '1' when can_send_whole = '1' and RX_MFB_SRC_RDY = '1' else '0';
319+
mfb_spl_rx_src_rdy <= '1' when can_send_whole = '1' and rx_fifo_mfb_src_rdy = '1' else '0';
265320

266-
RX_MFB_DST_RDY <= '1' when can_send_whole = '1' and mfb_spl_rx_dst_rdy = '1' else '0';
321+
rx_fifo_mfb_dst_rdy <= '1' when can_send_whole = '1' and mfb_spl_rx_dst_rdy = '1' else '0';
267322

268323
mfb_splitter_i : entity work.MFB_SPLITTER_SIMPLE
269324
generic map (
@@ -279,11 +334,11 @@ begin
279334

280335
RX_MFB_META => (others => '0'),
281336
RX_MFB_SEL => switch_fifoxm_do_dist,
282-
RX_MFB_DATA => RX_MFB_DATA,
283-
RX_MFB_SOF => RX_MFB_SOF,
284-
RX_MFB_EOF => RX_MFB_EOF,
285-
RX_MFB_SOF_POS => RX_MFB_SOF_POS,
286-
RX_MFB_EOF_POS => RX_MFB_EOF_POS,
337+
RX_MFB_DATA => rx_fifo_mfb_data,
338+
RX_MFB_SOF => rx_fifo_mfb_sof,
339+
RX_MFB_EOF => rx_fifo_mfb_eof,
340+
RX_MFB_SOF_POS => rx_fifo_mfb_sof_pos,
341+
RX_MFB_EOF_POS => rx_fifo_mfb_eof_pos,
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RX_MFB_SRC_RDY => mfb_spl_rx_src_rdy,
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RX_MFB_DST_RDY => mfb_spl_rx_dst_rdy,
289344

‎comp/mfb_tools/flow/splitter/mfb_splitter_gen.vhd‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -53,6 +53,12 @@ entity MFB_SPLITTER_GEN is
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-- Minimum value is 2!
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OUTPUT_FIFO_SIZE : integer := 8;
5555

56+
-- To enable optional MFB FIFOs at middle stages
57+
MID_MFB_FIFOS_EN : boolean := False;
58+
59+
-- Size of MFB FIFOs (in words)
60+
MFB_FIFO_DEPTH : natural := 512;
61+
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-- Output PIPE enable for all 2:1 splitters
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OUT_PIPE_EN : boolean := true;
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@@ -161,6 +167,8 @@ begin
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MFB_ITEM_WIDTH => MFB_ITEM_WIDTH,
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HDR_WIDTH => MVB_ITEM_WIDTH,
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MVB_OUTPUT_FIFO_SIZE => OUTPUT_FIFO_SIZE,
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IN_MFB_FIFO_EN => (s /= 0 and MID_MFB_FIFOS_EN),
171+
MFB_FIFO_DEPTH => MFB_FIFO_DEPTH,
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USE_OUTREG => OUT_PIPE_EN,
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DEVICE => DEVICE
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)

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