Deploying to gh-pages from @ 3eb4446 🚀

Author: jakubcabal

devel/ndk_core/doc/app.html

@@ -365,6 +365,16 @@ <h2>Ports and generics of the Application<a class="headerlink" href="#ports-and-
 <td><p>8</p></td>
 <td><p>ETH MFB: number of blocks in region</p></td>
 </tr>
+<tr class="row-even" id="vhdl-gengeneric-application_core-eth_rx_mtu"><td><p>ETH_RX_MTU</p></td>
+<td><p>integer_vector(ETH_STREAMS-1 downto 0)</p></td>
+<td><p>(others =&gt; 16383)</p></td>
+<td><p>ETH: Maximum allowed size of RX frame in bytes per Ethernet stream.</p></td>
+</tr>
+<tr class="row-odd" id="vhdl-gengeneric-application_core-eth_tx_mtu"><td><p>ETH_TX_MTU</p></td>
+<td><p>integer_vector(ETH_STREAMS-1 downto 0)</p></td>
+<td><p>(others =&gt; 16383)</p></td>
+<td><p>ETH: Maximum allowed size of TX frame in bytes per Ethernet stream.</p></td>
+</tr>
 <tr class="row-even" id="vhdl-gengeneric-application_core-pcie_endpoints"><td><p>PCIE_ENDPOINTS</p></td>
 <td><p>natural</p></td>
 <td><p>1</p></td>

devel/ndk_core/doc/pcie.html

@@ -400,6 +400,16 @@ <h2>The PCIe module entity<a class="headerlink" href="#the-pcie-module-entity" t
 <td><p>false</p></td>
 <td><p>Enable of XCV IP, for Xilinx only</p></td>
 </tr>
+<tr class="row-even" id="vhdl-gengeneric-pcie-pcie_core_dbg_enable"><td><p>PCIE_CORE_DBG_ENABLE</p></td>
+<td><p>boolean</p></td>
+<td><p>false</p></td>
+<td><p>Enable of PCIe core debug logic</p></td>
+</tr>
+<tr class="row-odd" id="vhdl-gengeneric-pcie-pcie_ctrl_dbg_enable"><td><p>PCIE_CTRL_DBG_ENABLE</p></td>
+<td><p>boolean</p></td>
+<td><p>false</p></td>
+<td><p>Enable of PCIe controller debug logic</p></td>
+</tr>
 <tr class="row-even" id="vhdl-gengeneric-pcie-misc_top2pcie_width"><td><p>MISC_TOP2PCIE_WIDTH</p></td>
 <td><p>natural</p></td>
 <td><p>1</p></td>