This directory contains the Windows host-side program used for voltage-transition measurement in the VolTune repository.
The program is intended to run from the MSYS2 environment and is used together with the FPGA-side voltage-control designs. It automatically writes the appropriate bitstream, configures the voltage-change parameters, records monitored voltage data, and saves settling-time-related results.
If an error occurs unexpectedly while running the test program, there is most likely a fatal problem with PMBus communication. If the test program is run again without powering off the KC705, the power settings of the KC705 may be corrupted, potentially causing fatal damage to the device.
Always restart the KC705 power before re-running the test.
This tool assumes the board has already completed normal bring-up and that the target rail is already enabled. It performs runtime voltage adjustment and sampled readback for the current prototype flow, not generic regulator initialization.
Incorrect voltage settings or unsafe PMBus operations may permanently damage the target hardware. Users are solely responsible for verifying all rail mappings, voltage limits, and command semantics against the original vendor documentation before running this tool.
Execute the following command on MSYS2 (C:\msys64\mingw64.exe).
cd <Repository top>
./msys_build.shIf you want to build them individually, execute the command as follows:
cd <Repository top>
mkdir build
cd build
cmake ../host
make -j voltage-measureIf the build is successful, the executable is generated under:
build/bin/voltage-measure.exe
The input file is a configuration file in a CSV-like format. Lines beginning with # and empty lines are ignored.
Each line should contain the following six pieces of information.
- Lane: Test voltage lane name
vccintvccauxvcc3v3vadfvcc2v5vcc1v5mgtavccmgtavttaccaux_iovccbrammgtvccaux
- Speed: Transceiver speed
none: no transceiver2.5g: 2.5 Gbps transceiver5g: 5 Gbps transceiver7.5g: 7.5 Gbps transceiver10g: 10 Gbps transceiver
- Device 0 initial voltage
- Device 0 target voltage
- Device 1 initial voltage
- Device 1 target voltage
For example, the following line means that, using bitstreams without transceivers, Device0 changes MGTAVCC from 1.0 V to 0.7 V, and Device1 changes MGTAVCC from 0.8 V to 1.0 V.
mgtavcc, none, 1.0, 0.7, 0.8, 1.0
When the program is executed, two types of CSV files are output.
- Result CSV: a file containing the time taken for each test to change and information about the settings. The output file name can be changed with the
-ooption. - Voltage Monitoring CSV: an information file of the voltage monitored by the FPGA. One CSV file is generated for each test. The output directory can be changed with the
-Ooption.
The following figure shows an example of the voltage-monitoring CSV output generated during a voltage-transition measurement.
voltage-measure.exe <CONFIG FILE> [OPTIONS]
<CONFIG FILE>: test configuration CSV file
-h: show help-b <directory>: bitstream directory path, default is./bitstream-c <MHz>: external clock frequency in MHz, default is125.000-e <error margin>: error margin of voltage to detect settling times, default is0.04(= 4%)-f <MHz>: FPGA base clock in MHz, default is100-n <size>: number of monitored voltage values to be read from the device, maximum is2048, default is100-o <file>: output result CSV file, default isv_result.csv-O <directory>: output voltage CSV directory-p <port>:hw_serverport-r <repeat>: number of times the same test is run repeatedly-s <speed>: PMBus speed, value is100k,400k, or1m, default is400k-u <URL>:hw_serverURL-x <xsdb path>:xsdbpath-y: start test without warning message-w <wait count>: time from setting the initial voltage and setting the target voltage, default is0.5[s]-sw: test software PowerManager only-hw: test hardware PowerManager only--log: show information-level log
This tool supports testing at no transceiver, 2.5 Gbps, 5 Gbps, 7.5 Gbps, and 10 Gbps.
- Connect the Windows PC, clock board Si5391, and KC705 boards.
- Create test input file
input1.csvfor no transceiver, 2.5 Gbps, 5 Gbps, and 10 Gbps.- The external clock for 2.5 Gbps, 5 Gbps, and 10 Gbps is 125 MHz, so you can test with only one configuration file.
- Create test input file
input2.csvfor 7.5 Gbps. - Set the clock output to 125 MHz in CBPro.
- Run:
voltage-measure.exe -b <Bitstream Directory> -o result1.csv -O result1 input1.csv- Set the clock output to 117.188 MHz in CBPro.
- Run:
voltage-measure.exe -b <Bitstream Directory> -o result2.csv -O result2 -c 117.188 input2.csvTo run one setting multiple times, use the -r option to specify the number of times to repeat the setting.
The following script automates the above steps:
It uses:
Results are output to the results folder.
The settling-time values reported by this tool can be cross-checked against external oscilloscope measurements.
In this repository, the primary automated measurement path uses PMBus-based voltage readback recorded by the FPGA and exported as CSV data. For validation, the same voltage transition can also be observed with an oscilloscope. The PMBus-based trace and the oscilloscope waveform reach the same target voltage and show the same overall transition trend. A timing offset can appear because the PMBus-based trace is derived from discrete sampled readback, while the oscilloscope provides higher-time-resolution analog sampling. For consistency across configurations, this repository uses the PMBus-based sampled readback for automated settling-time analysis.
args.hpp: CLI argument headerconfig.hpp: CSV-like input file headerresult.hpp: result data headerregs.hpp: register access utility headerargs.cpp: implementation ofargs.hppconfig.cpp: implementation ofconfig.hppresult.cpp: implementation ofresult.hppmain.cpp: main program
../README.md, parent host-side overview../../experiments/README.md, experiment inputs and helper files../../device/vivado/voltage/README.md, corresponding FPGA-side voltage-control designs
- Board-specific safe-voltage limits are not enforced generically by this tool and must be defined externally.
- This tool is intended for controller characterization and voltage-transition measurement rather than BER and power case-study evaluation.
- The host-side flow depends on the corresponding FPGA bitstreams and board setup being prepared correctly.
- Clock-board setup is not automated by this tool and must be prepared separately.


