diff --git a/crush/rtl/crush_cpu.v b/crush/rtl/crush_cpu.v index 1fe1d22..9e22f3b 100644 --- a/crush/rtl/crush_cpu.v +++ b/crush/rtl/crush_cpu.v @@ -3,18 +3,30 @@ module crush_cpu #( parameter integer INITIAL_PC = 0 ) ( - input wire clk_i, - input wire[31:0] dat_i, - output reg[31:0] dat_o, - input wire rst_i, - input wire ack_i, - input wire err_i, - input wire rty_i, - output reg stb_o, - output reg cyc_o, - output reg[31:0] adr_o, - output reg[3:0] sel_o, - output reg we_o + input wire clk_i, + input wire rst_i, + // Instruction wishbone bus + input wire[31:0] wb_inst_dat_i, + output reg[31:0] wb_inst_dat_o, + input wire wb_inst_ack_i, + input wire wb_inst_err_i, + input wire wb_inst_rty_i, + output reg wb_inst_stb_o, + output reg wb_inst_cyc_o, + output reg[31:0] wb_inst_adr_o, + output reg[3:0] wb_inst_sel_o, + output reg wb_inst_we_o, + // Data wishbone bus + input wire[31:0] wb_data_dat_i, + output reg[31:0] wb_data_dat_o, + input wire wb_data_ack_i, + input wire wb_data_err_i, + input wire wb_data_rty_i, + output reg wb_data_stb_o, + output reg wb_data_cyc_o, + output reg[31:0] wb_data_adr_o, + output reg[3:0] wb_data_sel_o, + output reg wb_data_we_o ); `include "params.vh" @@ -132,9 +144,9 @@ always @(posedge(clk_i)) begin end else begin case(state) STATE_FETCH: - if(ack_i) begin + if(wb_inst_ack_i) begin state <= STATE_REG_READ; - instruction <= dat_i; + instruction <= wb_inst_dat_i; end STATE_REG_READ: state <= STATE_EXECUTE; STATE_EXECUTE: begin @@ -142,9 +154,9 @@ always @(posedge(clk_i)) begin state_change <= 0; end STATE_MEMORY: - if(ack_i | (!mem_r_en & !mem_w_en)) begin + if(wb_data_ack_i | (!mem_r_en & !mem_w_en)) begin state <= STATE_REG_WRITE; - read_data <= dat_i; + read_data <= wb_data_dat_i; end else state_change <= 0; STATE_REG_WRITE: state <= STATE_FETCH; default: state <= STATE_FETCH; @@ -190,12 +202,19 @@ always @(*) begin pc_load = 0; pc_value = 32'hxxxx_xxxx; - stb_o = 0; - cyc_o = 0; - sel_o = 4'hx; - dat_o = 32'hxxxx_xxxx; - adr_o = 32'hxxxx_xxxx; - we_o = 1'hx; + wb_inst_stb_o = 0; + wb_inst_cyc_o = 0; + wb_inst_sel_o = 4'hx; + wb_inst_dat_o = 32'hxxxx_xxxx; + wb_inst_adr_o = 32'hxxxx_xxxx; + wb_inst_we_o = 1'hx; + + wb_data_stb_o = 0; + wb_data_cyc_o = 0; + wb_data_sel_o = 4'hx; + wb_data_dat_o = 32'hxxxx_xxxx; + wb_data_adr_o = 32'hxxxx_xxxx; + wb_data_we_o = 1'hx; alu_op_a = 32'hxxxx_xxxx; alu_op_b = 32'hxxxx_xxxx; @@ -205,11 +224,11 @@ always @(*) begin case(state) STATE_FETCH: begin - stb_o = 1; - cyc_o = 1; - adr_o = pc; - we_o = 0; - sel_o = 4'b1111; + wb_inst_stb_o = 1; + wb_inst_cyc_o = 1; + wb_inst_adr_o = pc; + wb_inst_we_o = 0; + wb_inst_sel_o = 4'b1111; end STATE_REG_READ: begin end @@ -219,29 +238,29 @@ always @(*) begin end STATE_MEMORY: begin if(mem_r_en) begin - stb_o = 1; - cyc_o = 1; - adr_o = alu_out_r & ~32'h0000_0003; - we_o = 0; - sel_o = 4'b1111; + wb_data_stb_o = 1; + wb_data_cyc_o = 1; + wb_data_adr_o = alu_out_r & ~32'h0000_0003; + wb_data_we_o = 0; + wb_data_sel_o = 4'b1111; end if(mem_w_en) begin - stb_o = 1; - cyc_o = 1; - adr_o = alu_out_r & ~32'h0000_0003; + wb_data_stb_o = 1; + wb_data_cyc_o = 1; + wb_data_adr_o = alu_out_r & ~32'h0000_0003; case(funct3) - FUNCT3_SW: dat_o = r_out2; - FUNCT3_SH: dat_o = r_out2 << (16 * alu_out_r[1]); - FUNCT3_SB: dat_o = r_out2 << (8 * alu_out_r[0 +: 2]); - default: dat_o = r_out2; + FUNCT3_SW: wb_data_dat_o = r_out2; + FUNCT3_SH: wb_data_dat_o = r_out2 << (16 * alu_out_r[1]); + FUNCT3_SB: wb_data_dat_o = r_out2 << (8 * alu_out_r[0 +: 2]); + default: wb_data_dat_o = r_out2; endcase - we_o = 1; + wb_data_we_o = 1; case(funct3) - FUNCT3_SW: sel_o = 4'b1111; - FUNCT3_SH: sel_o = 4'b0011 << (2 * alu_out_r[1]); - FUNCT3_SB: sel_o = 4'b0001 << alu_out_r[0 +: 2]; - default: sel_o = 4'bxxxx; + FUNCT3_SW: wb_data_sel_o = 4'b1111; + FUNCT3_SH: wb_data_sel_o = 4'b0011 << (2 * alu_out_r[1]); + FUNCT3_SB: wb_data_sel_o = 4'b0001 << alu_out_r[0 +: 2]; + default: wb_data_sel_o = 4'bxxxx; endcase end end diff --git a/crush/sim/cpu_tb.v b/crush/sim/cpu_tb.v index 854f0d9..985a26f 100644 --- a/crush/sim/cpu_tb.v +++ b/crush/sim/cpu_tb.v @@ -13,46 +13,68 @@ module cpu_tb; reg clk = 1; reg reset = 1; -wire stb_o; -wire cyc_o; -wire[31:0] adr_o; -wire[3:0] sel_o; -wire[31:0] dat_i; -wire[31:0] dat_o; -wire we_o; -wire ack_i; -wire err_i = 0; -wire rty_i = 0; + +wire wb_inst_stb_o; +wire wb_inst_cyc_o; +wire[31:0] wb_inst_adr_o; +wire[3:0] wb_inst_sel_o; +wire[31:0] wb_inst_dat_i; +wire[31:0] wb_inst_dat_o; +wire wb_inst_we_o; +wire wb_inst_ack_i; +wire wb_inst_err_i = 0; +wire wb_inst_rty_i = 0; + +wire wb_data_stb_o; +wire wb_data_cyc_o; +wire[31:0] wb_data_adr_o; +wire[3:0] wb_data_sel_o; +wire[31:0] wb_data_dat_i; +wire[31:0] wb_data_dat_o; +wire wb_data_we_o; +wire wb_data_ack_i; +wire wb_data_err_i = 0; +wire wb_data_rty_i = 0; crush_cpu #(.INITIAL_PC('h1000_0000)) dut ( .clk_i(clk), - .dat_i(dat_i), - .dat_o(dat_o), .rst_i(reset), - .ack_i(ack_i), - .err_i(err_i), - .rty_i(rty_i), - .stb_o(stb_o), - .cyc_o(cyc_o), - .adr_o(adr_o), - .sel_o(sel_o), - .we_o(we_o) + .wb_inst_dat_i(wb_inst_dat_i), + .wb_inst_dat_o(wb_inst_dat_o), + .wb_inst_ack_i(wb_inst_ack_i), + .wb_inst_err_i(wb_inst_err_i), + .wb_inst_rty_i(wb_inst_rty_i), + .wb_inst_stb_o(wb_inst_stb_o), + .wb_inst_cyc_o(wb_inst_cyc_o), + .wb_inst_adr_o(wb_inst_adr_o), + .wb_inst_sel_o(wb_inst_sel_o), + .wb_inst_we_o(wb_inst_we_o), + .wb_data_dat_i(wb_data_dat_i), + .wb_data_dat_o(wb_data_dat_o), + .wb_data_ack_i(wb_data_ack_i), + .wb_data_err_i(wb_data_err_i), + .wb_data_rty_i(wb_data_rty_i), + .wb_data_stb_o(wb_data_stb_o), + .wb_data_cyc_o(wb_data_cyc_o), + .wb_data_adr_o(wb_data_adr_o), + .wb_data_sel_o(wb_data_sel_o), + .wb_data_we_o(wb_data_we_o) ); -wire flash_ack_o; +wire wb_inst_flash_ack_o; memory_infer #(.BASE_ADDRESS('h1000_0000), .SIZE('h20_0000)) flash_emulator ( .clk_i(clk), .rst_i(reset), - .stb_i(stb_o), - .cyc_i(cyc_o), - .adr_i(adr_o), - .sel_i(sel_o), - .dat_i(dat_o), - .dat_o(dat_i), - .we_i(we_o), - .ack_o(flash_ack_o), - .err_o(err_i), - .rty_o(rty_i) + .stb_i(wb_inst_stb_o), + .cyc_i(wb_inst_cyc_o), + .adr_i(wb_inst_adr_o), + .sel_i(wb_inst_sel_o), + .dat_i(wb_inst_dat_o), + .dat_o(wb_inst_dat_i), + .we_i(wb_inst_we_o), + .ack_o(wb_inst_flash_ack_o), + .err_o(wb_inst_err_i), + .rty_o(wb_inst_rty_i) ); initial begin @@ -74,44 +96,80 @@ initial begin end end -wire memory_ack_o; -memory_infer #(.BASE_ADDRESS('h2000_0000), .SIZE('h4000)) memory ( +wire wb_data_init_data_ack_o; +memory_infer #(.BASE_ADDRESS('h2000_0000), .SIZE('h4000)) init_data ( + .clk_i(clk), + .rst_i(reset), + .stb_i(wb_data_stb_o), + .cyc_i(wb_data_cyc_o), + .adr_i(wb_data_adr_o), + .sel_i(wb_data_sel_o), + .dat_i(wb_data_dat_o), + .dat_o(wb_data_dat_i), + .we_i(wb_data_we_o), + .ack_o(wb_data_init_data_ack_o), + .err_o(wb_data_err_i), + .rty_o(wb_data_rty_i) +); + +initial begin + string path; + if($value$plusargs("INIT_DATA_PATH=%s", path)) begin + integer file; + integer length; + + $display("Reading initialised data memory contents from %s", path); + + file = $fopen(path, "rb"); + length = $fread(init_data.mem, file); + $fclose(file); + + $display("Read %0d bytes", length); + end else begin + $error("The INIT_DATA_PATH plus arg must be set"); + $stop; + end +end + +wire wb_data_memory_ack_o; +memory_infer #(.BASE_ADDRESS('h3000_0000), .SIZE('h4000)) memory ( .clk_i(clk), .rst_i(reset), - .stb_i(stb_o), - .cyc_i(cyc_o), - .adr_i(adr_o), - .sel_i(sel_o), - .dat_i(dat_o), - .dat_o(dat_i), - .we_i(we_o), - .ack_o(memory_ack_o), - .err_o(err_i), - .rty_o(rty_i) + .stb_i(wb_data_stb_o), + .cyc_i(wb_data_cyc_o), + .adr_i(wb_data_adr_o), + .sel_i(wb_data_sel_o), + .dat_i(wb_data_dat_o), + .dat_o(wb_data_dat_i), + .we_i(wb_data_we_o), + .ack_o(wb_data_memory_ack_o), + .err_o(wb_data_err_i), + .rty_o(wb_data_rty_i) ); -wire control_ack_o; +wire wb_data_control_ack_o; control #( - .BASE_ADDRESS('h3000_0000), - .MEMORY_BASE_ADDRESS('h2000_0000), + .BASE_ADDRESS('h4000_0000), + .MEMORY_BASE_ADDRESS('h3000_0000), .MEMORY_SIZE('h4000) ) control ( .clk_i(clk), .rst_i(reset), - .stb_i(stb_o), - .cyc_i(cyc_o), - .adr_i(adr_o), - .sel_i(sel_o), - .dat_i(dat_o), - .dat_o(dat_i), - .we_i(we_o), - .ack_o(control_ack_o), - .err_o(err_i), - .rty_o(rty_i), + .stb_i(wb_data_stb_o), + .cyc_i(wb_data_cyc_o), + .adr_i(wb_data_adr_o), + .sel_i(wb_data_sel_o), + .dat_i(wb_data_dat_o), + .dat_o(wb_data_dat_i), + .we_i(wb_data_we_o), + .ack_o(wb_data_control_ack_o), + .err_o(wb_data_err_i), + .rty_o(wb_data_rty_i), .memory(memory.mem) ); -assign ack_i = flash_ack_o | memory_ack_o | control_ack_o; +assign wb_inst_ack_i = wb_inst_flash_ack_o; +assign wb_data_ack_i = wb_data_init_data_ack_o | wb_data_memory_ack_o | wb_data_control_ack_o; always begin #0.5 clk <= !clk; diff --git a/crush_example/crush_example.core b/crush_example/crush_example.core index 45e83a8..218fd2c 100644 --- a/crush_example/crush_example.core +++ b/crush_example/crush_example.core @@ -6,9 +6,12 @@ name: ::crush_example:0.0.1 filesets: rtl: files: - - fw/binary/crush-blinky.data: + - fw/binary/crush-blinky-instruction.data: file_type: user - copyto: fw.data + copyto: inst.data + - fw/binary/crush-blinky-data.data: + file_type: user + copyto: data.data - rtl/memory.v - rtl/memory_ice40_spram.v - rtl/top.v diff --git a/crush_example/fw/CMakeLists.txt b/crush_example/fw/CMakeLists.txt index 9ae9e21..7fa5dff 100644 --- a/crush_example/fw/CMakeLists.txt +++ b/crush_example/fw/CMakeLists.txt @@ -12,7 +12,13 @@ set_target_properties(crush-blinky PROPERTIES LINK_DEPENDS ${CMAKE_CURRENT_SOURC string(REPLACE "-gcc" "-objcopy" objcopy_name ${CMAKE_C_COMPILER}) find_program(objcopy_program ${objcopy_name} REQUIRED) + add_custom_command(TARGET crush-blinky POST_BUILD - COMMAND ${objcopy_program} -O verilog -j .mem -j .bss -j .stack --adjust-vma -0x10000000 --verilog-data-width 4 crush-blinky ${CMAKE_CURRENT_LIST_DIR}/binary/crush-blinky.data + COMMAND ${objcopy_program} -O verilog -j .instruction_memory --verilog-data-width 4 crush-blinky ${CMAKE_CURRENT_LIST_DIR}/binary/crush-blinky-instruction.data WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} ) + +add_custom_command(TARGET crush-blinky POST_BUILD + COMMAND ${objcopy_program} -O verilog -j .memory -j .stack --verilog-data-width 4 crush-blinky ${CMAKE_CURRENT_LIST_DIR}/binary/crush-blinky-data.data + WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} +) diff --git a/crush_example/fw/binary/crush-blinky-data.data b/crush_example/fw/binary/crush-blinky-data.data new file mode 100755 index 0000000..e69de29 diff --git a/crush_example/fw/binary/crush-blinky.data b/crush_example/fw/binary/crush-blinky-instruction.data similarity index 93% rename from crush_example/fw/binary/crush-blinky.data rename to crush_example/fw/binary/crush-blinky-instruction.data index 79d4dd7..3a7525f 100755 --- a/crush_example/fw/binary/crush-blinky.data +++ b/crush_example/fw/binary/crush-blinky-instruction.data @@ -1,5 +1,5 @@ @00000000 -00000117 50010113 004000EF FF010113 +10000117 40010113 004000EF FF010113 00112623 008000EF 0000006F FF010113 00912223 00112623 00812423 00000493 07C000EF 0014C493 00050413 00048593 diff --git a/crush_example/fw/crush.ld b/crush_example/fw/crush.ld index eec4140..87dc30b 100644 --- a/crush_example/fw/crush.ld +++ b/crush_example/fw/crush.ld @@ -3,29 +3,28 @@ ENTRY(start) MEMORY { - mem (rwx): ORIGIN = 0x10000000, LENGTH = 0x800 * 4 + instruction_memory (x): ORIGIN = 0x00000000, LENGTH = 0x400 * 4 + memory (rw): ORIGIN = 0x10000000, LENGTH = 0x400 * 4 } SECTIONS { - .mem : { + .instruction_memory : { . = ALIGN(4); KEEP(*(.start)) *(.text .text.*) - *(.rodata .rodata*) . = ALIGN(4); - *(.data .data.*); - } > mem + } > instruction_memory - .bss (NOLOAD) : { + .memory : { . = ALIGN(4); - bss_start = .; *(.bss .bss.*) *(COMMON) + *(.data .data.*); + *(.rodata .rodata*) . = ALIGN(4); - bss_end = .; - } > mem - + } > memory + .stack : { . = 1K; /* stack size */ /* Calling conventions require 16 byte aligned stack pointer @@ -33,6 +32,6 @@ SECTIONS */ . = ALIGN(16); stack_start = .; - } > mem + } > memory } diff --git a/crush_example/rtl/top.v b/crush_example/rtl/top.v index 33f8f12..506b479 100644 --- a/crush_example/rtl/top.v +++ b/crush_example/rtl/top.v @@ -11,77 +11,124 @@ module top ( wire rst_i = !BTN_N; wire clk = CLK; -wire stb_o; -wire cyc_o; -wire[31:0] adr_o; -wire[3:0] sel_o; -wire[31:0] dat_i; -wire[31:0] dat_o; -wire we_o; -wire ack_i; -wire err_i; -wire rty_i; +wire wb_inst_stb_o; +wire wb_inst_cyc_o; +wire[31:0] wb_inst_adr_o; +wire[3:0] wb_inst_sel_o; +wire[31:0] wb_inst_dat_i; +wire[31:0] wb_inst_dat_o; +wire wb_inst_we_o; +wire wb_inst_ack_i; +wire wb_inst_err_i; +wire wb_inst_rty_i; -crush_cpu #(.INITIAL_PC('h1000_0000)) cpu ( +wire wb_data_stb_o; +wire wb_data_cyc_o; +wire[31:0] wb_data_adr_o; +wire[3:0] wb_data_sel_o; +wire[31:0] wb_data_dat_i; +wire[31:0] wb_data_dat_o; +wire wb_data_we_o; +wire wb_data_ack_i; +wire wb_data_err_i; +wire wb_data_rty_i; + +crush_cpu #(.INITIAL_PC('h0000_0000)) cpu ( .clk_i(clk), - .dat_i(dat_i), - .dat_o(dat_o), .rst_i(rst_i), - .ack_i(ack_i), - .err_i(err_i), - .rty_i(rty_i), - .stb_o(stb_o), - .cyc_o(cyc_o), - .adr_o(adr_o), - .sel_o(sel_o), - .we_o(we_o) + .wb_inst_dat_i(wb_inst_dat_i), + .wb_inst_dat_o(wb_inst_dat_o), + .wb_inst_ack_i(wb_inst_ack_i), + .wb_inst_err_i(wb_inst_err_i), + .wb_inst_rty_i(wb_inst_rty_i), + .wb_inst_stb_o(wb_inst_stb_o), + .wb_inst_cyc_o(wb_inst_cyc_o), + .wb_inst_adr_o(wb_inst_adr_o), + .wb_inst_sel_o(wb_inst_sel_o), + .wb_inst_we_o(wb_inst_we_o), + .wb_data_dat_i(wb_data_dat_i), + .wb_data_dat_o(wb_data_dat_o), + .wb_data_ack_i(wb_data_ack_i), + .wb_data_err_i(wb_data_err_i), + .wb_data_rty_i(wb_data_rty_i), + .wb_data_stb_o(wb_data_stb_o), + .wb_data_cyc_o(wb_data_cyc_o), + .wb_data_adr_o(wb_data_adr_o), + .wb_data_sel_o(wb_data_sel_o), + .wb_data_we_o(wb_data_we_o) ); -wire memory_ack_o; -wire memory_rty_o; -wire memory_err_o; +wire wb_inst_instruction_memory_ack_o; +wire wb_inst_instruction_memory_rty_o; +wire wb_inst_instruction_memory_err_o; + memory_infer #( + .BASE_ADDRESS('h0000_0000), + .SIZE('h400), + .READMEMH_FILE("inst.data") + ) instruction_memory ( + .clk_i(clk), + .rst_i(rst_i), + .stb_i(wb_inst_stb_o), + .cyc_i(wb_inst_cyc_o), + .adr_i(wb_inst_adr_o), + .sel_i(wb_inst_sel_o), + .dat_i(wb_inst_dat_o), + .dat_o(wb_inst_dat_i), + .we_i (wb_inst_we_o), + .ack_o(wb_inst_instruction_memory_ack_o), + .err_o(wb_inst_instruction_memory_err_o), + .rty_o(wb_inst_instruction_memory_rty_o) + ); + +wire wb_data_memory_ack_o; +wire wb_data_memory_rty_o; +wire wb_data_memory_err_o; memory_infer #( .BASE_ADDRESS('h1000_0000), - .SIZE('h800), - .READMEMH_FILE("fw.data") + .SIZE('h400), + .READMEMH_FILE("data.data") ) memory ( .clk_i(clk), .rst_i(rst_i), - .stb_i(stb_o), - .cyc_i(cyc_o), - .adr_i(adr_o), - .sel_i(sel_o), - .dat_i(dat_o), - .dat_o(dat_i), - .we_i (we_o), - .ack_o(memory_ack_o), - .err_o(memory_err_o), - .rty_o(memory_rty_o) + .stb_i(wb_data_stb_o), + .cyc_i(wb_data_cyc_o), + .adr_i(wb_data_adr_o), + .sel_i(wb_data_sel_o), + .dat_i(wb_data_dat_o), + .dat_o(wb_data_dat_i), + .we_i (wb_data_we_o), + .ack_o(wb_data_memory_ack_o), + .err_o(wb_data_memory_err_o), + .rty_o(wb_data_memory_rty_o) ); -wire gpio_ack_o; -wire gpio_rty_o; -wire gpio_err_o; +wire wb_data_gpio_ack_o; +wire wb_data_gpio_rty_o; +wire wb_data_gpio_err_o; wire [5:0] unused; gpio #(.BASE_ADDRESS('h4000_0000)) gpio ( .clk_i(clk), .rst_i(rst_i), - .stb_i(stb_o), - .cyc_i(cyc_o), - .adr_i(adr_o), - .sel_i(sel_o), - .dat_i(dat_o), - .dat_o(dat_i), - .we_i(we_o), - .ack_o(gpio_ack_o), - .err_o(gpio_err_o), - .rty_o(gpio_rty_o), + .stb_i(wb_data_stb_o), + .cyc_i(wb_data_cyc_o), + .adr_i(wb_data_adr_o), + .sel_i(wb_data_sel_o), + .dat_i(wb_data_dat_o), + .dat_o(wb_data_dat_i), + .we_i(wb_data_we_o), + .ack_o(wb_data_gpio_ack_o), + .err_o(wb_data_gpio_err_o), + .rty_o(wb_data_gpio_rty_o), .pin_input({{7{1'b0}}, BTN1}), .pin_output({unused, LED2, LED1}) ); -assign ack_i = memory_ack_o | gpio_ack_o; -assign err_i = memory_err_o | gpio_err_o; -assign rty_i = memory_rty_o | gpio_rty_o; +assign wb_data_ack_i = wb_data_memory_ack_o | wb_data_gpio_ack_o; +assign wb_data_err_i = wb_data_memory_err_o | wb_data_gpio_err_o; +assign wb_data_rty_i = wb_data_memory_rty_o | wb_data_gpio_rty_o; + +assign wb_inst_ack_i = wb_inst_instruction_memory_ack_o; +assign wb_inst_err_i = wb_inst_instruction_memory_err_o; +assign wb_inst_rty_i = wb_inst_instruction_memory_rty_o; endmodule diff --git a/tools/compliance/crush/env/link.ld b/tools/compliance/crush/env/link.ld index 3e23571..c500ffd 100644 --- a/tools/compliance/crush/env/link.ld +++ b/tools/compliance/crush/env/link.ld @@ -3,8 +3,9 @@ ENTRY(rvtest_entry_point) MEMORY { - rom (rx): ORIGIN = 0x10000000, LENGTH = 0x200000 - ram (rw): ORIGIN = 0x20000000, LENGTH = 0x4000 + rom (x): ORIGIN = 0x10000000, LENGTH = 0x200000 + data (rw): ORIGIN = 0x20000000, LENGTH = 0x4000 + ram (rw): ORIGIN = 0x30000000, LENGTH = 0x4000 } SECTIONS @@ -12,7 +13,6 @@ SECTIONS .text : { . = ALIGN(4); *(.text .text.*) - *(.rodata .rodata*) . = ALIGN(4); } > rom @@ -20,9 +20,10 @@ SECTIONS . = ALIGN(4); _srelocate = .; *(.data .data.*); + *(.rodata .rodata*) . = ALIGN(4); _erelocate = .; - } > ram AT> rom + } > ram AT> data _etext = LOADADDR(.data); diff --git a/tools/compliance/crush/env/model_test.h b/tools/compliance/crush/env/model_test.h index 16e4cd9..36e0d99 100644 --- a/tools/compliance/crush/env/model_test.h +++ b/tools/compliance/crush/env/model_test.h @@ -33,7 +33,7 @@ */ #define RVMODEL_HALT \ la x1, rvtest_sig_begin; \ - la x2, 0x30000000; \ + la x2, 0x40000000; \ sw x1, 0(x2); \ la x1, rvtest_sig_end; \ sw x1, 4(x2); \ @@ -47,7 +47,7 @@ * needs to be run prior to running the tests. */ #define RVMODEL_BOOT \ - /* Copy data section from flash to RAM */ \ + /* Copy data section from initialised data memory to RAM */ \ la x1, _srelocate; \ la x2, _erelocate; \ la x3, _etext; \ diff --git a/tools/compliance/crush/riscof_crush.py b/tools/compliance/crush/riscof_crush.py index 752f3c2..3a27a97 100644 --- a/tools/compliance/crush/riscof_crush.py +++ b/tools/compliance/crush/riscof_crush.py @@ -85,9 +85,16 @@ def doRunTest(self, test_entry): ) utils.shellCommand(cmd).run(cwd=working_directory) + # The executable binary binary_path = os.path.join(working_directory, 'test.bin') - binary_cmd = f'{self.compiler_name_prefix}-objcopy -O binary -j .text -j .data -j .bss --reverse-bytes=4 test.elf {binary_path}' + binary_cmd = f'{self.compiler_name_prefix}-objcopy -O binary -j .text -j .bss --reverse-bytes=4 test.elf {binary_path}' utils.shellCommand(binary_cmd).run(cwd=working_directory) - sim_cmd = f'vvp -n {self.dut_exe} +SIGNATURE_PATH={sig_file} +BINARY_PATH={binary_path}' + # The initialised data + init_data_path = os.path.join(working_directory, 'init_data.bin') + init_data_cmd = f'{self.compiler_name_prefix}-objcopy -O binary -j .data --reverse-bytes=4 test.elf {init_data_path}' + utils.shellCommand(init_data_cmd).run(cwd=working_directory) + + + sim_cmd = f'vvp -n {self.dut_exe} +SIGNATURE_PATH={sig_file} +BINARY_PATH={binary_path} +INIT_DATA_PATH={init_data_path}' utils.shellCommand(sim_cmd).run(cwd=working_directory)