Status of case (in)equality operators (=== and !==)

[quark17]

It appears that the Verilog === and !== operators (for 4-state comparison, simulation only) are defined in Prelude and can be used in BH. I don't know how well that works -- they turn into calls to PrimEQ3 (and not . PrimEQ3) and, for example, I don't know if maybe there are optimizations that look for PrimEQ that aren't being applied when they should?

The other issue is that it's not recognized by the BSV parser: you get an error that === is unexpected, as it's not an operator that the BSV parser knows about. Line 3817 of CVParser.lhs has a comment where it would be included in the list of operators. (Note that there are other Verilog/SV operators commented out there, such as wildcard comparisons =?= and !?=.)

A workaround for BSV is to refer to the operator as a function with an escaped name:

function Bool eq3 (Bit#(n) x, Bit#(n) y);
  return \=== (x,y);
endfunction

Or define a function like eq3 (in BH or BSV) and use that in place of the operator.

We should figure out if support for this operator is good and, if so, add it to the BSV parser (as a user was asking about it).