Organization-MultiCPU/top.v at master · AndersonALAC/Organization-MultiCPU · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    22:21:01 06/29/2020
// Design Name:
// Module Name:    top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top(
    input clk,
    input clk_CPU,
    input rst,

    output [31:0] PC,
    output [31:0] Inst,
    output [31:0] Data_write,
    output [31:0] Data_read,
    output [31:0] Addr,
    output mem_w,
    output [4:0] state,
    output [2:0] RAMCtrl
    );

    MultiCPU cpu(.clk(clk_CPU),
                 .reset(rst),
                 .inst_out(Inst),
                 .PC_out(PC),
                 .mem_w(mem_w),
                 .Addr_out(Addr),
                 .Data_in(Data_read),
                 .Data_out(Data_write),
                 .state(state),
                 .MIO_ready(1'b1),
                 .RAMCtrl(RAMCtrl)
                );

    RAM ram(.clk(clk),
            .addr(Addr[9:0]),
            .din(Data_write),
            .RAMCtrl(RAMCtrl),
            .we(mem_w),
            .dout(Data_read)
           );


endmodule