Author: Ahasan Ullah Khalid (aukhalid02@gmail.com)
| Name | Type | Dimension | Default | Description |
|---|---|---|---|---|
| WIDTH | int | 1 | Bit width of the data bus | |
| STAGES | int | 2 | Number of synchronization stages (min 2 recommended) | |
| RESET_VALUE | logic [WIDTH-1:0] | '0 | Value to load during reset |
| Name | Direction | Type | Dimension | Description |
|---|---|---|---|---|
| clk_i | input | logic | Destination clock domain | |
| arst_ni | input | logic | Active-low asynchronous reset | |
| en_i | input | logic | Enable signal for synchronization stages | |
| data_i | input | logic [WIDTH-1:0] | Asynchronous input data | |
| data_o | output | logic [WIDTH-1:0] | Synchronized output data |
The adn_common_synchronizer module is a generic multi-stage flip-flop synchronizer designed to safely transfer asynchronous signals between different clock domains. It mitigates metastability issues by passing the input data through a configurable number of sequential stages before outputting the synchronized signal.
This module is primarily used when a signal originates in one clock domain and must be sampled by logic in a different clock domain. By utilizing a chain of flip-flops, it provides the necessary settling time for the signal to stabilize, effectively preventing metastability from propagating into the destination domain's logic. It is ideal for control signals, status flags, and single-bit handshaking protocols where data integrity across clock boundaries is critical.
| REVISION | DATE | AUTHOR | DESCRIPTION |
|---|---|---|---|
| 0.1 | 2026-07-28 | Ahasan Ullah Khalid | Initial version |
| 1.0 | 2026-07-28 | Ahasan Ullah Khalid | Stable release |
| 1.1 | 2026-08-01 | Foez Ahmed | Ratified |
Author : Ahasan Ullah Khalid (aukhalid02@gmail.com)